ganimede-rework #20
@ -53,7 +53,8 @@ begin
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techmap_ram_inst : entity techmap.syncram_2p
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generic map(tech => tech,
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abits => address_bits,
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dbits => fifo_width
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dbits => fifo_width,
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sepclk => 1
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)
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port map(
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rclk => out_clk,
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@ -97,8 +98,8 @@ begin
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if rising_edge(in_clk) and valid_in = '1' and buffer_full = '0' then
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write_pointer <= std_logic_vector(unsigned(write_pointer) + 1);
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end if;
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if rising_edge(out_clk) then
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if ready_in = '1' and buffer_empty = '0' and unsigned(read_pointer) + 1 /= unsigned(write_pointer) then
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if falling_edge(out_clk) then
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if ready_in = '1' and buffer_empty = '0' then
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read_pointer <= std_logic_vector(unsigned(read_pointer) + 1);
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valid_out <= '1';
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else
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