src/fifo_buffer/fifo_deserializer.vhd

@@ -6,7 +6,8 @@ use ieee.numeric_std.all;
 entity fifo_deserializer is
   generic (
     output_width : natural := 8;
-    input_width  : natural := 8
+    input_width  : natural := 8;
+    endianess    : integer := 0  -- 0: little endian, 1: big endian
   );
   port (
     rst, clk : in std_logic;
@@ -54,7 +55,11 @@ begin
       st.count <= 0;
     elsif valid_in = '1' and ready_in = '1' then
       st.count <= st.count + 1;
-      st.data((st.count + 1) * input_width - 1 downto st.count * input_width) <= data_in;
+      if endianess = 0 then
+        st.data((out_over_in - st.count) * input_width  - 1 downto (out_over_in - st.count - 1) * input_width) <= data_in;
+      else
+        st.data((st.count + 1) * input_width - 1 downto st.count * input_width) <= data_in;
+      end if;
     end if;
   end if;
 end process seq_proc;

src/fifo_buffer/fifo_serializer.vhd

@@ -7,7 +7,7 @@ entity fifo_serializer is
   generic (
     output_width : natural := 8;
     input_width  : natural := 8;
-    endianess    : integer := 1
+    endianess    : integer := 0 -- 0: little endian, 1: big endian
   );
   port (
     rst, clk : in std_logic;
@@ -41,9 +41,9 @@ begin
   valid_out <= st.valid;
   if st.count <= in_over_out and st.valid = '1' then
     if endianess = 0 then
-      data_out <= st.data((st.count + 1) * output_width - 1 downto st.count * output_width);
-    else
       data_out <= st.data((input_width - st.count * output_width) - 1 downto input_width - (st.count + 1) * output_width);
+    else
+      data_out <= st.data((st.count + 1) * output_width - 1 downto st.count * output_width);
     end if;
   else
     data_out <= (others => '0');

src/ganimede/ganimede.vhd

@@ -31,6 +31,7 @@ architecture rtl of ganimede_toplevel is
   signal buffer_to_socbridge_driver : fifo_interface_t;
   signal ip_to_socbridge_driver : ip_to_socbridge_driver_t;
   signal socbridge_clk : std_logic;
+  signal ganimede_to_ip_reset : std_logic;
 
   --signal gan_socbridge_WE_in : std_logic;
   --signal gan_socbridge_WE_out : std_logic;
@@ -41,7 +42,7 @@ begin
   --- INTERNAL CONNECTIONS ---
   ip_to_socbridge_driver.fifo <= buffer_to_socbridge_driver;
   ip_to_socbridge_driver.flush <= ip_to_ganimede.socbridge.flush;
-
+  ganimede_to_ip_reset <= rst or ip_to_ganimede.socbridge.flush;
   --- DRIVER INSTANTIATION ---
   socbridge_driver_inst: entity gan_socbridge.socbridge_driver
     port map(
@@ -80,13 +81,13 @@ begin
 
   fifo_buffer_to_ip_inst : entity gan_buffer.fifo_buffer
     generic map (
-      buffer_size => 1024
+      buffer_size => 2*1024
       --tech => 60
     )
     port map(
       in_clk => socbridge_clk,
       out_clk => clk,
-      rst => rst,
+      rst => ganimede_to_ip_reset,
       ready_in => ip_to_ganimede.socbridge.fifo.ready,
       ready_out => buffer_to_socbridge_driver.ready,
       valid_in => socbridge_driver_to_buffer.valid,
@@ -97,7 +98,7 @@ begin
 
   fifo_buffer_from_ip_inst : entity gan_buffer.fifo_buffer
     generic map (
-      buffer_size => 1024
+      buffer_size => 2*1024
 --      tech => 60
     )
     port map(

src/socbridge/socbridge_driver.vhd

@@ -540,7 +540,8 @@ begin
       trans_st.write.curr_state <= trans_write_next_state;
       case trans_st.write.curr_state is
         when IDLE =>
-          if controller_to_socbridge_driver.request = '1' and controller_to_socbridge_driver.instruction = WRITE then
+          if controller_to_socbridge_driver.request = '1' and controller_to_socbridge_driver.instruction = WRITE 
+             and trans_st.write.curr_inst.request = '0' then
             trans_st.write.curr_inst <= controller_to_socbridge_driver;
           else 
           end if;