src/fifo_buffer/fifo_deserializer.vhd

@@ -25,14 +25,13 @@ constant out_over_in : natural := output_width / input_width;
 type state_t is record
   count : integer;
   data : std_logic_vector(output_width - 1 downto 0);
-  bad_bad: integer;
 end record state_t;
 signal st : state_t;
 begin
 
 comb_proc: process(rst,clk,valid_in,ready_in,data_in,st)
 begin
-  if st.count = out_over_in and st.bad_bad <= 560 then
+  if st.count = out_over_in then
     valid_out <= '1';
   else 
     valid_out <= '0';
@@ -50,13 +49,11 @@ begin
   if rst = '1' then
     st.count <= 0;
     st.data <= (others => '0');
-    st.bad_bad <= 0;
   elsif (rising_edge(clk)) then
     if st.count = out_over_in then
       st.count <= 0;
     elsif valid_in = '1' and ready_in = '1' then
       st.count <= st.count + 1;
-      st.bad_bad <= st.bad_bad + 1;
       st.data((st.count + 1) * input_width - 1 downto st.count * input_width) <= data_in;
     end if;
   end if;