ganimede-rework #20
@ -604,13 +604,11 @@ begin
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trans_st.read.curr_inst.request <= '0';
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trans_st.read.curr_inst.address <= (others => '0');
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trans_st.read.curr_inst.seq_mem_access_count <= 0;
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trans_st.read.curr_inst.instruction <= NO_OP;
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trans_st.read.is_first_word <= '1';
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trans_st.write.curr_state <= IDLE;
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trans_st.write.curr_inst.request <= '0';
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trans_st.write.curr_inst.address <= (others => '0');
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trans_st.write.curr_inst.seq_mem_access_count <= 0;
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trans_st.write.curr_inst.instruction <= NO_OP;
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trans_st.write.is_first_word <= '1';
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elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then
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trans_st.read.curr_state <= trans_read_next_state;
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@ -619,7 +617,9 @@ begin
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when IDLE =>
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if controller_to_socbridge_driver.request = '1' and controller_to_socbridge_driver.instruction = WRITE
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and trans_st.write.curr_inst.request = '0' then
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trans_st.write.curr_inst <= controller_to_socbridge_driver;
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trans_st.write.curr_inst.request <= controller_to_socbridge_driver.request;
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trans_st.write.curr_inst.address <= controller_to_socbridge_driver.address;
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trans_st.write.curr_inst.seq_mem_access_count <= controller_to_socbridge_driver.seq_mem_access_count;
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else
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end if;
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trans_st.write.is_first_word <= '1';
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@ -642,7 +642,6 @@ begin
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trans_st.write.curr_inst.request <= '0';
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trans_st.write.curr_inst.address <= (others => '0');
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trans_st.write.curr_inst.seq_mem_access_count <= 0;
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trans_st.write.curr_inst.instruction <= NO_OP;
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end if;
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if trans_st.write.curr_inst.seq_mem_access_count mod 256 = 0 then
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trans_st.write.is_first_word <= '1';
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@ -657,7 +656,9 @@ begin
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case trans_st.read.curr_state is
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when IDLE =>
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if controller_to_socbridge_driver.request = '1' and controller_to_socbridge_driver.instruction = READ then
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trans_st.read.curr_inst <= controller_to_socbridge_driver;
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trans_st.read.curr_inst.request <= controller_to_socbridge_driver.request;
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trans_st.read.curr_inst.address <= controller_to_socbridge_driver.address;
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trans_st.read.curr_inst.seq_mem_access_count <= controller_to_socbridge_driver.seq_mem_access_count;
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else
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end if;
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trans_st.read.is_first_word <= '1';
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@ -678,7 +679,6 @@ begin
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trans_st.read.curr_inst.request <= '0';
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trans_st.read.curr_inst.address <= (others => '0');
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trans_st.read.curr_inst.seq_mem_access_count <= 0;
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trans_st.read.curr_inst.instruction <= NO_OP;
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end if;
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if trans_st.read.curr_inst.seq_mem_access_count mod 256 = 0 then
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trans_st.read.is_first_word <= '1';
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@ -23,8 +23,15 @@ package socbridge_driver_pkg is
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--- TRANSLATOR ---
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type ctrl_inst_state_t is (IDLE, SEND, SEND_ACCEPTED, AWAIT);
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type ctrl_inst_t is record
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request : std_logic;
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address : std_logic_vector(address_width - 1 downto 0);
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seq_mem_access_count : integer;
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instruction : instruction_command_t;
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end record ctrl_inst_t;
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type ctrl_inst_state_rec_t is record
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curr_inst : controller_to_socbridge_driver_t;
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curr_inst : ctrl_inst_t;
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curr_state : ctrl_inst_state_t;
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is_first_word : std_logic;
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end record ctrl_inst_state_rec_t;
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