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ganimede-rework #20

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kryddan wants to merge 25 commits from ganimede-rework into ganimede-single-issue
pull from: ganimede-rework
merge into: kryddan:ganimede-single-issue
Conversation 0 Commits 25 Files Changed 10 +17 -5
2 changed files with 17 additions and 5 deletions
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11
src/fifo_buffer/fifo_deserializer.vhd
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@ -25,18 +25,23 @@ constant out_over_in : natural := output_width / input_width;
type state_t is record type state_t is record
count : integer; count : integer;
data : std_logic_vector(output_width - 1 downto 0); data : std_logic_vector(output_width - 1 downto 0);
bad_bad: integer;
end record state_t; end record state_t;
signal st : state_t; signal st : state_t;
begin begin
comb_proc: process(rst,clk,valid_in,ready_in,data_in,st) comb_proc: process(rst,clk,valid_in,ready_in,data_in,st)
begin begin
if st.count = out_over_in then if st.count = out_over_in and st.bad_bad <= 560 then
valid_out <= '1'; valid_out <= '1';
else else
valid_out <= '0'; valid_out <= '0';
end if; end if;
ready_out <= ready_in ; if not (st.count = out_over_in) and ready_in = '1' then
ready_out <= '1';
else
ready_out <= '0';
end if;
data_out <= st.data; data_out <= st.data;
end process comb_proc; end process comb_proc;
@ -45,11 +50,13 @@ begin
if rst = '1' then if rst = '1' then
st.count <= 0; st.count <= 0;
st.data <= (others => '0'); st.data <= (others => '0');
st.bad_bad <= 0;
elsif (rising_edge(clk)) then elsif (rising_edge(clk)) then
if st.count = out_over_in then if st.count = out_over_in then
st.count <= 0; st.count <= 0;
elsif valid_in = '1' and ready_in = '1' then elsif valid_in = '1' and ready_in = '1' then
st.count <= st.count + 1; st.count <= st.count + 1;
st.bad_bad <= st.bad_bad + 1;
st.data((st.count + 1) * input_width - 1 downto st.count * input_width) <= data_in; st.data((st.count + 1) * input_width - 1 downto st.count * input_width) <= data_in;
end if; end if;
end if; end if;

11
src/fifo_buffer/fifo_serializer.vhd
View File

@ -6,7 +6,8 @@ use ieee.numeric_std.all;
entity fifo_serializer is entity fifo_serializer is
generic ( generic (
output_width : natural := 8; output_width : natural := 8;
input_width : natural := 8 input_width : natural := 8;
endianess : integer := 1
); );
port ( port (
rst, clk : in std_logic; rst, clk : in std_logic;
@ -32,14 +33,18 @@ begin
comb_proc: process(rst,clk,valid_in,ready_in,data_in,st) comb_proc: process(rst,clk,valid_in,ready_in,data_in,st)
begin begin
if st.count = 0 and ready_in = '1' then if st.valid = '0' and valid_in = '0' then
ready_out <= '1'; ready_out <= '1';
else else
ready_out <= '0'; ready_out <= '0';
end if; end if;
valid_out <= st.valid; valid_out <= st.valid;
if st.count <= in_over_out and st.valid = '1' then if st.count <= in_over_out and st.valid = '1' then
data_out <= st.data((st.count + 1) * output_width - 1 downto st.count * output_width); if endianess = 0 then
data_out <= st.data((st.count + 1) * output_width - 1 downto st.count * output_width);
else
data_out <= st.data((input_width - st.count * output_width) - 1 downto input_width - (st.count + 1) * output_width);
end if;
else else
data_out <= (others => '0'); data_out <= (others => '0');
end if; end if;