src/fifo_buffer/fifo_deserializer.vhd

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+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+use ieee.numeric_std.all;
+
+entity fifo_deserializer is
+  generic (
+    output_width : natural := 8;
+    input_width  : natural := 8
+  );
+  port (
+    rst, clk : in std_logic;
+    ready_in : in std_logic;
+    ready_out : out std_logic;
+    valid_in : in std_logic;
+    valid_out : out std_logic;
+    data_in : in std_logic_vector(input_width - 1 downto 0);
+    data_out : out std_logic_vector(output_width - 1 downto 0)
+  );
+end entity fifo_deserializer;
+
+architecture rtl of fifo_deserializer is
+
+constant out_over_in : natural := output_width / input_width;
+type state_t is record
+  count : integer;
+  data : std_logic_vector(output_width - 1 downto 0);
+end record state_t;
+signal st : state_t;
+begin
+
+comb_proc: process(rst,clk,valid_in,ready_in,data_in,st)
+begin
+  if st.count = out_over_in then
+    valid_out <= '1';
+  else 
+    valid_out <= '0';
+  end if;
+  ready_out <= ready_in ;
+  data_out <= st.data;
+end process comb_proc; 
+
+seq_proc: process(clk, rst)
+begin
+  if rst = '1' then
+    st.count <= 0;
+    st.data <= (others => '0');
+  elsif (rising_edge(clk)) then
+    if st.count = out_over_in then
+      st.count <= 0;
+    elsif valid_in = '1' and ready_in = '1' then
+      st.count <= st.count + 1;
+      st.data((st.count + 1) * input_width - 1 downto st.count * input_width) <= data_in;
+    end if;
+  end if;
+end process seq_proc;
+
+end architecture rtl;

src/fifo_buffer/fifo_serializer.vhd

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+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+use ieee.numeric_std.all;
+
+entity fifo_serializer is
+  generic (
+    output_width : natural := 8;
+    input_width  : natural := 8
+  );
+  port (
+    rst, clk : in std_logic;
+    ready_in : in std_logic;
+    ready_out : out std_logic;
+    valid_in : in std_logic;
+    valid_out : out std_logic;
+    data_in : in std_logic_vector(input_width - 1 downto 0);
+    data_out : out std_logic_vector(output_width - 1 downto 0)
+  );
+end entity fifo_serializer;
+
+architecture rtl of fifo_serializer is
+
+constant in_over_out : natural := input_width / output_width - 1;
+type state_t is record
+  count : integer;
+  valid : std_logic;
+  data : std_logic_vector(input_width - 1 downto 0);
+end record state_t;
+signal st : state_t;
+begin
+
+comb_proc: process(rst,clk,valid_in,ready_in,data_in,st)
+begin
+  if st.count = 0 and ready_in = '1' then
+    ready_out <= '1';
+  else 
+    ready_out <= '0';
+  end if;
+  valid_out <= st.valid;
+  if st.count <= in_over_out and st.valid = '1' then
+    data_out <= st.data((st.count + 1) * output_width - 1 downto st.count * output_width);
+  else
+    data_out <= (others => '0');
+  end if;
+end process comb_proc; 
+
+seq_proc: process(clk, rst)
+begin
+  if rst = '1' then
+    st.count <= 0;
+    st.valid <= '0';
+    st.data <= (others => '0');
+  elsif (rising_edge(clk)) then
+    if valid_in = '1' and st.count = 0 then
+      st.valid <= '1';
+      st.data <= data_in;
+    elsif valid_in = '1' and st.count = in_over_out and ready_in = '1' then
+      st.count <= 0;
+      st.valid <= '1';
+      st.data <= data_in;
+    elsif st.count = in_over_out and ready_in = '1' then
+      st.valid <= '0';
+      st.count <= 0;
+    elsif ready_in = '1' and st.valid = '1' then
+      st.count <= st.count + 1;
+    end if;
+  end if;
+end process seq_proc;
+
+end architecture rtl;