From 9c0ef57be85cc111df9c0f343fd57bd9033f408c Mon Sep 17 00:00:00 2001 From: Adam Date: Mon, 24 Feb 2025 17:13:00 +0100 Subject: [PATCH 1/8] Started working on io for control unit --- src/control_unit.vhd | 34 ++++++++++++++++++++++++++++++++++ src/io_type_pkg.vhd | 9 +++++++++ 2 files changed, 43 insertions(+) create mode 100644 src/control_unit.vhd diff --git a/src/control_unit.vhd b/src/control_unit.vhd new file mode 100644 index 0000000..48273a7 --- /dev/null +++ b/src/control_unit.vhd @@ -0,0 +1,34 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.MATH_REAL.all; +library work; +use work.io_types.all; + +entity control_unit is + + port ( + clk, rst: in std_logic; + address_read_in, address_write_in: in control_unit_ext_t.address; + address_read_out, address_write_out: in control_unit_ext_t.address); + words_to_read_in: in std_logic_vector(control_unit_ext_t.seq_read_count); + words_to_write_in: in std_logic_vector(control_unit_ext_t.seq_write_count); + ); + +end entity control_unit; + +architecture behave of control_unit is + +begin + + main_proc: process(clk) + begin + if rising_edge(clk) then + if rst = '0' then + + else + + end if; + end if; + end process main_proc; + +end architecture behave; diff --git a/src/io_type_pkg.vhd b/src/io_type_pkg.vhd index 3afb8f0..bfac5b1 100644 --- a/src/io_type_pkg.vhd +++ b/src/io_type_pkg.vhd @@ -15,6 +15,15 @@ package io_types is socbridge: ext_protocol_def_t; end record interface_inst_t; + constant number_of_drivers = 3; + + type control_unit_ext_t is record + interface_id_count: in std_logic_vector(number_of_drivers)) downto 0); + address: in std_logic_vector(32 downto 0); + seq_write_count: in std_logic_vector(7 downto 0); + seq_read_count: in std_logic_vector(7 downto 0); + end record control_unit_format; + --- PROTOCOL INFORMATION --- constant interface_inst : interface_inst_t := ( socbridge => ("SoCBridge ", 8, 2, 2) -- 2.43.0 From 84f9101d8fada6cc420214c2a503a750f1863f59 Mon Sep 17 00:00:00 2001 From: Adam Date: Tue, 25 Feb 2025 17:11:29 +0100 Subject: [PATCH 2/8] Started work on control functionality, not tested --- src/control_unit.vhd | 47 ++++++++++++++++++++++++++++++++++---------- src/io_type_pkg.vhd | 17 +++++++++++----- 2 files changed, 49 insertions(+), 15 deletions(-) diff --git a/src/control_unit.vhd b/src/control_unit.vhd index 48273a7..668d123 100644 --- a/src/control_unit.vhd +++ b/src/control_unit.vhd @@ -8,27 +8,54 @@ entity control_unit is port ( clk, rst: in std_logic; - address_read_in, address_write_in: in control_unit_ext_t.address; - address_read_out, address_write_out: in control_unit_ext_t.address); - words_to_read_in: in std_logic_vector(control_unit_ext_t.seq_read_count); - words_to_write_in: in std_logic_vector(control_unit_ext_t.seq_write_count); + control_in: in control_unit_in_t; + control_out: out control_unit_out_t ); end entity control_unit; architecture behave of control_unit is - + type state_t is record + address: std_logic_vector(address_width - 1 downto 0); + seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); + curr_driver: std_logic_vector(number_of_drivers - 1 downto 0); --one-hot encoded, 0 means disabled + ready: std_logic + end record type_name; + + signal state: state_t := (others => '0', + others => '0', + others => '0', + '1'); + begin - - main_proc: process(clk) + + comb_proc: process(control_in, control_out, state) + variable ored: std_logic := '0'; + begin + ready_reduction: for i in 0 to number_of_drivers loop + ored <= ored or control_in.active_driver(i); + end loop ready_reduction; + ready <= ored; + end process comb_proc; + + sync_proc: process(clk, state) begin if rising_edge(clk) then if rst = '0' then - + state <= (others => '0', + others => '0', + others => '0'); else - + if state.ready = '1' then + state.address <= control_in.address; + state.seq_mem_access_count <= control_in.seq_mem_access_count; + state.curr_driver <= control_in.driver_id; + end if; + control_out.driver_id <= state.curr_driver; + control_out.address <= state.address; + control_out.seq_mem_access_count <= state.seq_mem_access_count; end if; end if; - end process main_proc; + end process sync_proc; end architecture behave; diff --git a/src/io_type_pkg.vhd b/src/io_type_pkg.vhd index bfac5b1..4af6ee1 100644 --- a/src/io_type_pkg.vhd +++ b/src/io_type_pkg.vhd @@ -16,14 +16,21 @@ package io_types is end record interface_inst_t; constant number_of_drivers = 3; + constant address_width = 32; + constant seq_vector_length = 8; - type control_unit_ext_t is record - interface_id_count: in std_logic_vector(number_of_drivers)) downto 0); - address: in std_logic_vector(32 downto 0); - seq_write_count: in std_logic_vector(7 downto 0); - seq_read_count: in std_logic_vector(7 downto 0); + type control_unit_out_t is record + driver_id: std_logic_vector(number_of_drivers - 1 downto 0); + address: std_logic_vector(address_width - 1 downto 0); + seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); + ready: std_logic end record control_unit_format; + type control_unit_in_t is record + driver_id, active_driver: std_logic_vector(number_of_drivers - 1 downto 0); + address: std_logic_vector(address_width - 1 downto 0); + seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0) + end record control_unit_format; --- PROTOCOL INFORMATION --- constant interface_inst : interface_inst_t := ( socbridge => ("SoCBridge ", 8, 2, 2) -- 2.43.0 From 966bdb85d1f71d120dc41bacd5cd1a9594c8734d Mon Sep 17 00:00:00 2001 From: Adam Magnusson Date: Wed, 26 Feb 2025 18:19:54 +0100 Subject: [PATCH 3/8] started working on control unit testbench --- src/control_unit.vhd | 20 ++++++++--------- src/control_unit_tb.vhd | 49 +++++++++++++++++++++++++++++++++++++++++ src/io_type_pkg.vhd | 14 ++++++------ 3 files changed, 65 insertions(+), 18 deletions(-) create mode 100644 src/control_unit_tb.vhd diff --git a/src/control_unit.vhd b/src/control_unit.vhd index 668d123..f49b14a 100644 --- a/src/control_unit.vhd +++ b/src/control_unit.vhd @@ -19,16 +19,13 @@ architecture behave of control_unit is address: std_logic_vector(address_width - 1 downto 0); seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); curr_driver: std_logic_vector(number_of_drivers - 1 downto 0); --one-hot encoded, 0 means disabled - ready: std_logic - end record type_name; + ready: std_logic; + end record state_t; - signal state: state_t := (others => '0', - others => '0', - others => '0', - '1'); + signal state: state_t; begin - + comb_proc: process(control_in, control_out, state) variable ored: std_logic := '0'; begin @@ -36,6 +33,9 @@ begin ored <= ored or control_in.active_driver(i); end loop ready_reduction; ready <= ored; + control_out.driver_id <= state.curr_driver; + control_out.address <= state.address; + control_out.seq_mem_access_count <= state.seq_mem_access_count; end process comb_proc; sync_proc: process(clk, state) @@ -44,16 +44,14 @@ begin if rst = '0' then state <= (others => '0', others => '0', - others => '0'); + others => '0', + '1'); else if state.ready = '1' then state.address <= control_in.address; state.seq_mem_access_count <= control_in.seq_mem_access_count; state.curr_driver <= control_in.driver_id; end if; - control_out.driver_id <= state.curr_driver; - control_out.address <= state.address; - control_out.seq_mem_access_count <= state.seq_mem_access_count; end if; end if; end process sync_proc; diff --git a/src/control_unit_tb.vhd b/src/control_unit_tb.vhd new file mode 100644 index 0000000..14c9d15 --- /dev/null +++ b/src/control_unit_tb.vhd @@ -0,0 +1,49 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.MATH_REAL.all; +library work; +use work.io_types.all; + +entity control_unit_tb +end entity control_unit_tb; + +architecture tb of control_unit_tb is + + constant cycle := 10 ns; + signal clock := '0'; + signal finished: std_logic; + + + component control_unit is + port( + clk, rst: in std_logic; + control_in: in control_unit_in_t; + control_out: out control_unit_out_t); + end component control_unit; + +begin + + clock <= not clock after cycle / 2 when finished /= '1'; + + control_unit_inst: control_unit + port map( + clk => clock, + rst => reset, + + ); + +stimulus_proc: process +begin + finished <= '0'; + + finished <= '1'; +end process stimulus_proc; + +monitor_proc: process +begin + finished <= '0'; + + finished <= '1'; +end process monitor_proc; + +end architecture tb; diff --git a/src/io_type_pkg.vhd b/src/io_type_pkg.vhd index 4af6ee1..ff8c6c6 100644 --- a/src/io_type_pkg.vhd +++ b/src/io_type_pkg.vhd @@ -15,22 +15,22 @@ package io_types is socbridge: ext_protocol_def_t; end record interface_inst_t; - constant number_of_drivers = 3; - constant address_width = 32; - constant seq_vector_length = 8; + constant number_of_drivers: natural := 3; + constant address_width: natural := 32; + constant seq_vector_length: natural := 8; type control_unit_out_t is record driver_id: std_logic_vector(number_of_drivers - 1 downto 0); address: std_logic_vector(address_width - 1 downto 0); seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); - ready: std_logic - end record control_unit_format; + ready: std_logic; + end record control_unit_out_t; type control_unit_in_t is record driver_id, active_driver: std_logic_vector(number_of_drivers - 1 downto 0); address: std_logic_vector(address_width - 1 downto 0); - seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0) - end record control_unit_format; + seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); + end record control_unit_in_t; --- PROTOCOL INFORMATION --- constant interface_inst : interface_inst_t := ( socbridge => ("SoCBridge ", 8, 2, 2) -- 2.43.0 From 142e92f43decbd309310f3527a670310b07a0266 Mon Sep 17 00:00:00 2001 From: Adam Magnusson Date: Fri, 28 Feb 2025 17:03:13 +0100 Subject: [PATCH 4/8] testbench almost done, needs debugging --- src/control_unit.vhd | 18 ++++++------ src/control_unit_tb.vhd | 62 +++++++++++++++++++++++++++++++++-------- 2 files changed, 60 insertions(+), 20 deletions(-) diff --git a/src/control_unit.vhd b/src/control_unit.vhd index f49b14a..b236a27 100644 --- a/src/control_unit.vhd +++ b/src/control_unit.vhd @@ -26,13 +26,13 @@ architecture behave of control_unit is begin - comb_proc: process(control_in, control_out, state) + comb_proc: process(control_in, state) variable ored: std_logic := '0'; begin - ready_reduction: for i in 0 to number_of_drivers loop - ored <= ored or control_in.active_driver(i); + ready_reduction: for i in 0 to number_of_drivers - 1 loop + ored := ored or control_in.active_driver(i); end loop ready_reduction; - ready <= ored; + state.ready <= ored; control_out.driver_id <= state.curr_driver; control_out.address <= state.address; control_out.seq_mem_access_count <= state.seq_mem_access_count; @@ -41,11 +41,11 @@ begin sync_proc: process(clk, state) begin if rising_edge(clk) then - if rst = '0' then - state <= (others => '0', - others => '0', - others => '0', - '1'); + if rst = '1' then + state <= ((others => '0'), + (others => '0'), + (others => '0'), + '0'); else if state.ready = '1' then state.address <= control_in.address; diff --git a/src/control_unit_tb.vhd b/src/control_unit_tb.vhd index 14c9d15..beda742 100644 --- a/src/control_unit_tb.vhd +++ b/src/control_unit_tb.vhd @@ -4,15 +4,27 @@ use IEEE.MATH_REAL.all; library work; use work.io_types.all; -entity control_unit_tb +entity control_unit_tb is end entity control_unit_tb; architecture tb of control_unit_tb is - constant cycle := 10 ns; - signal clock := '0'; - signal finished: std_logic; - + constant cycle: Time := 10 ns; + signal clock: std_logic := '0'; + signal stim_finished, mon_finished: std_logic; + signal reset: std_logic; + signal control_input: control_unit_in_t := ( + (others => '0'), + (others => '0'), + (others => '0'), + (others => '0')); + signal control_output: control_unit_out_t := ( + (others => '0'), + (others => '0'), + (others => '0'), + '0'); + signal current_driver : std_logic_vector(2 downto 0) := "000"; + shared variable word_counter: natural := 0; component control_unit is port( @@ -23,27 +35,55 @@ architecture tb of control_unit_tb is begin - clock <= not clock after cycle / 2 when finished /= '1'; + clock <= not clock after cycle / 2 when (stim_finished and mon_finished) /= '1'; control_unit_inst: control_unit port map( clk => clock, rst => reset, - + control_in => control_input, + control_out => control_output ); stimulus_proc: process begin - finished <= '0'; + stim_finished <= '0'; + + wait for cycle; + + control_input.driver_id <= "010"; + control_input.active_driver <= "000"; + control_input.address <= x"F0F0F0F0"; + control_input.seq_mem_access_count <= "00000111"; - finished <= '1'; + report "entering loop with word_counter" & integer'image(word_counter); + for_loop: for i in word_counter - 1 downto 0 loop + wait for cycle; + report "word counter is " & integer'image(word_counter); + end loop for_loop; + + control_input.active_driver <= "000"; + + stim_finished <= '1'; + wait until mon_finished = '1'; + wait; end process stimulus_proc; monitor_proc: process begin - finished <= '0'; + mon_finished <= '0'; - finished <= '1'; + wait for cycle; + + wait for cycle; + assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity warning; + assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity warning; + wait until word_counter = 0; + assert control_output.ready = '1' report "control_unit did not signal ready" severity warning; + + mon_finished <= '1'; + wait until stim_finished = '1'; + wait; end process monitor_proc; end architecture tb; -- 2.43.0 From 25431d2da2cb640bb0fdda7ba68e01522093427a Mon Sep 17 00:00:00 2001 From: Adam Date: Mon, 3 Mar 2025 16:46:02 +0100 Subject: [PATCH 5/8] testbench debgging --- src/control_unit.vhd | 11 +++++++---- src/control_unit_tb.vhd | 42 ++++++++++++++--------------------------- 2 files changed, 21 insertions(+), 32 deletions(-) diff --git a/src/control_unit.vhd b/src/control_unit.vhd index b236a27..6c67401 100644 --- a/src/control_unit.vhd +++ b/src/control_unit.vhd @@ -23,19 +23,21 @@ architecture behave of control_unit is end record state_t; signal state: state_t; + shared variable ored: std_logic; + begin comb_proc: process(control_in, state) - variable ored: std_logic := '0'; begin + ored := '0'; ready_reduction: for i in 0 to number_of_drivers - 1 loop ored := ored or control_in.active_driver(i); end loop ready_reduction; - state.ready <= ored; control_out.driver_id <= state.curr_driver; control_out.address <= state.address; control_out.seq_mem_access_count <= state.seq_mem_access_count; + control_out.ready <= state.ready; end process comb_proc; sync_proc: process(clk, state) @@ -45,9 +47,10 @@ begin state <= ((others => '0'), (others => '0'), (others => '0'), - '0'); + '1'); else - if state.ready = '1' then + state.ready <= not ored; + if ored = '0' then state.address <= control_in.address; state.seq_mem_access_count <= control_in.seq_mem_access_count; state.curr_driver <= control_in.driver_id; diff --git a/src/control_unit_tb.vhd b/src/control_unit_tb.vhd index beda742..2787f70 100644 --- a/src/control_unit_tb.vhd +++ b/src/control_unit_tb.vhd @@ -1,6 +1,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.MATH_REAL.all; +use ieee.numeric_std.all; library work; use work.io_types.all; @@ -11,50 +12,41 @@ architecture tb of control_unit_tb is constant cycle: Time := 10 ns; signal clock: std_logic := '0'; - signal stim_finished, mon_finished: std_logic; - signal reset: std_logic; + signal reset: std_logic := '0'; signal control_input: control_unit_in_t := ( (others => '0'), (others => '0'), (others => '0'), - (others => '0')); + "00000011"); signal control_output: control_unit_out_t := ( (others => '0'), (others => '0'), - (others => '0'), - '0'); + (others => '1'), + '1'); signal current_driver : std_logic_vector(2 downto 0) := "000"; shared variable word_counter: natural := 0; - component control_unit is - port( - clk, rst: in std_logic; - control_in: in control_unit_in_t; - control_out: out control_unit_out_t); - end component control_unit; - begin - clock <= not clock after cycle / 2 when (stim_finished and mon_finished) /= '1'; + clock <= not clock after cycle / 2; - control_unit_inst: control_unit + control_unit_inst: entity work.control_unit port map( clk => clock, rst => reset, control_in => control_input, control_out => control_output - ); + ); stimulus_proc: process begin - stim_finished <= '0'; - wait for cycle; control_input.driver_id <= "010"; control_input.active_driver <= "000"; control_input.address <= x"F0F0F0F0"; control_input.seq_mem_access_count <= "00000111"; + word_counter := 3; report "entering loop with word_counter" & integer'image(word_counter); for_loop: for i in word_counter - 1 downto 0 loop @@ -63,26 +55,20 @@ begin end loop for_loop; control_input.active_driver <= "000"; - - stim_finished <= '1'; - wait until mon_finished = '1'; + report "Stim process done"; wait; end process stimulus_proc; monitor_proc: process begin - mon_finished <= '0'; wait for cycle; wait for cycle; - assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity warning; - assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity warning; - wait until word_counter = 0; - assert control_output.ready = '1' report "control_unit did not signal ready" severity warning; - - mon_finished <= '1'; - wait until stim_finished = '1'; + assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error; + assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error; + wait for 5 * cycle; + report "Monitor process done"; wait; end process monitor_proc; -- 2.43.0 From f8b93e6d06806e5f258b12c158dcf9ba0039a45d Mon Sep 17 00:00:00 2001 From: Adam Date: Mon, 3 Mar 2025 16:59:06 +0100 Subject: [PATCH 6/8] testbench works --- src/control_unit_tb.vhd | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/control_unit_tb.vhd b/src/control_unit_tb.vhd index 2787f70..0f2ce51 100644 --- a/src/control_unit_tb.vhd +++ b/src/control_unit_tb.vhd @@ -27,8 +27,15 @@ architecture tb of control_unit_tb is shared variable word_counter: natural := 0; begin - - clock <= not clock after cycle / 2; + + clock_proc: process + begin + for i in 0 to 50 loop + wait for cycle / 2; + clock <= not clock; + end loop; + wait; + end process clock_proc; control_unit_inst: entity work.control_unit port map( @@ -47,6 +54,8 @@ begin control_input.address <= x"F0F0F0F0"; control_input.seq_mem_access_count <= "00000111"; word_counter := 3; + wait for cycle; + current_driver <= "010"; report "entering loop with word_counter" & integer'image(word_counter); for_loop: for i in word_counter - 1 downto 0 loop -- 2.43.0 From 044060364d65142f97151dfe2fad4218210863d6 Mon Sep 17 00:00:00 2001 From: Adam Magnusson Date: Tue, 4 Mar 2025 14:54:15 +0100 Subject: [PATCH 7/8] Control unit tested and seems to work for the requirements of the basic version --- src/control_unit.vhd | 7 +++++-- src/control_unit_tb.vhd | 15 +++++++++++---- src/io_type_pkg.vhd | 3 ++- 3 files changed, 18 insertions(+), 7 deletions(-) diff --git a/src/control_unit.vhd b/src/control_unit.vhd index 6c67401..64cbe0c 100644 --- a/src/control_unit.vhd +++ b/src/control_unit.vhd @@ -19,7 +19,7 @@ architecture behave of control_unit is address: std_logic_vector(address_width - 1 downto 0); seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); curr_driver: std_logic_vector(number_of_drivers - 1 downto 0); --one-hot encoded, 0 means disabled - ready: std_logic; + ready, is_write: std_logic; end record state_t; signal state: state_t; @@ -38,6 +38,7 @@ begin control_out.address <= state.address; control_out.seq_mem_access_count <= state.seq_mem_access_count; control_out.ready <= state.ready; + control_out.is_write <= state.is_write; end process comb_proc; sync_proc: process(clk, state) @@ -47,13 +48,15 @@ begin state <= ((others => '0'), (others => '0'), (others => '0'), - '1'); + '1', + '0'); else state.ready <= not ored; if ored = '0' then state.address <= control_in.address; state.seq_mem_access_count <= control_in.seq_mem_access_count; state.curr_driver <= control_in.driver_id; + state.is_write <= control_in.is_write; end if; end if; end if; diff --git a/src/control_unit_tb.vhd b/src/control_unit_tb.vhd index 0f2ce51..3921f52 100644 --- a/src/control_unit_tb.vhd +++ b/src/control_unit_tb.vhd @@ -17,12 +17,14 @@ architecture tb of control_unit_tb is (others => '0'), (others => '0'), (others => '0'), - "00000011"); + (others => '0'), + '0'); signal control_output: control_unit_out_t := ( (others => '0'), (others => '0'), (others => '1'), - '1'); + '1', + '0'); signal current_driver : std_logic_vector(2 downto 0) := "000"; shared variable word_counter: natural := 0; @@ -52,7 +54,8 @@ begin control_input.driver_id <= "010"; control_input.active_driver <= "000"; control_input.address <= x"F0F0F0F0"; - control_input.seq_mem_access_count <= "00000111"; + control_input.seq_mem_access_count <= "00000011"; + control_input.is_write <= '1'; word_counter := 3; wait for cycle; current_driver <= "010"; @@ -60,7 +63,7 @@ begin report "entering loop with word_counter" & integer'image(word_counter); for_loop: for i in word_counter - 1 downto 0 loop wait for cycle; - report "word counter is " & integer'image(word_counter); + report "words remaining are " & integer'image(i); end loop for_loop; control_input.active_driver <= "000"; @@ -76,7 +79,11 @@ begin wait for cycle; assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error; assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error; + assert control_output.is_write = '0' report "Incorrect memory op from control_unit" severity error; + wait for 5 * cycle; + reset <= '1'; + report "Monitor process done"; wait; end process monitor_proc; diff --git a/src/io_type_pkg.vhd b/src/io_type_pkg.vhd index ff8c6c6..ea50409 100644 --- a/src/io_type_pkg.vhd +++ b/src/io_type_pkg.vhd @@ -23,13 +23,14 @@ package io_types is driver_id: std_logic_vector(number_of_drivers - 1 downto 0); address: std_logic_vector(address_width - 1 downto 0); seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); - ready: std_logic; + ready, is_write: std_logic; end record control_unit_out_t; type control_unit_in_t is record driver_id, active_driver: std_logic_vector(number_of_drivers - 1 downto 0); address: std_logic_vector(address_width - 1 downto 0); seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); + is_write: std_logic; end record control_unit_in_t; --- PROTOCOL INFORMATION --- constant interface_inst : interface_inst_t := ( -- 2.43.0 From 94e158d52c1bdd2b77f90912eb64143b2f68f8da Mon Sep 17 00:00:00 2001 From: Adam Magnusson Date: Tue, 4 Mar 2025 16:33:49 +0100 Subject: [PATCH 8/8] Made instruction a byte instead of a bit --- src/control_unit.vhd | 9 +++++---- src/control_unit_tb.vhd | 8 ++++---- src/io_type_pkg.vhd | 6 ++++-- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/control_unit.vhd b/src/control_unit.vhd index 64cbe0c..7c4095b 100644 --- a/src/control_unit.vhd +++ b/src/control_unit.vhd @@ -19,7 +19,8 @@ architecture behave of control_unit is address: std_logic_vector(address_width - 1 downto 0); seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); curr_driver: std_logic_vector(number_of_drivers - 1 downto 0); --one-hot encoded, 0 means disabled - ready, is_write: std_logic; + ready: std_logic; + instruction: std_logic_vector(inst_word_width - 1 downto 0); end record state_t; signal state: state_t; @@ -38,7 +39,7 @@ begin control_out.address <= state.address; control_out.seq_mem_access_count <= state.seq_mem_access_count; control_out.ready <= state.ready; - control_out.is_write <= state.is_write; + control_out.instruction <= state.instruction; end process comb_proc; sync_proc: process(clk, state) @@ -49,14 +50,14 @@ begin (others => '0'), (others => '0'), '1', - '0'); + x"00"); else state.ready <= not ored; if ored = '0' then state.address <= control_in.address; state.seq_mem_access_count <= control_in.seq_mem_access_count; state.curr_driver <= control_in.driver_id; - state.is_write <= control_in.is_write; + state.instruction <= control_in.instruction; end if; end if; end if; diff --git a/src/control_unit_tb.vhd b/src/control_unit_tb.vhd index 3921f52..62eefd8 100644 --- a/src/control_unit_tb.vhd +++ b/src/control_unit_tb.vhd @@ -18,13 +18,13 @@ architecture tb of control_unit_tb is (others => '0'), (others => '0'), (others => '0'), - '0'); + x"00"); signal control_output: control_unit_out_t := ( (others => '0'), (others => '0'), (others => '1'), '1', - '0'); + x"00"); signal current_driver : std_logic_vector(2 downto 0) := "000"; shared variable word_counter: natural := 0; @@ -55,7 +55,7 @@ begin control_input.active_driver <= "000"; control_input.address <= x"F0F0F0F0"; control_input.seq_mem_access_count <= "00000011"; - control_input.is_write <= '1'; + control_input.instruction <= x"81"; word_counter := 3; wait for cycle; current_driver <= "010"; @@ -79,7 +79,7 @@ begin wait for cycle; assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error; assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error; - assert control_output.is_write = '0' report "Incorrect memory op from control_unit" severity error; + assert control_output.instruction = x"81" report "Incorrect memory op from control_unit" severity error; wait for 5 * cycle; reset <= '1'; diff --git a/src/io_type_pkg.vhd b/src/io_type_pkg.vhd index ea50409..6238419 100644 --- a/src/io_type_pkg.vhd +++ b/src/io_type_pkg.vhd @@ -18,19 +18,21 @@ package io_types is constant number_of_drivers: natural := 3; constant address_width: natural := 32; constant seq_vector_length: natural := 8; + constant inst_word_width: natural := 8; type control_unit_out_t is record driver_id: std_logic_vector(number_of_drivers - 1 downto 0); address: std_logic_vector(address_width - 1 downto 0); seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); - ready, is_write: std_logic; + ready: std_logic; + instruction: std_logic_vector(inst_word_width - 1 downto 0); end record control_unit_out_t; type control_unit_in_t is record driver_id, active_driver: std_logic_vector(number_of_drivers - 1 downto 0); address: std_logic_vector(address_width - 1 downto 0); seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); - is_write: std_logic; + instruction: std_logic_vector(inst_word_width - 1 downto 0); end record control_unit_in_t; --- PROTOCOL INFORMATION --- constant interface_inst : interface_inst_t := ( -- 2.43.0