library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
library ganimede;
use ganimede.io_types.all;
library socbridge;
use socbridge.socbridge_driver_tb_pkg.all;
library controller;

entity control_socbridge_tb is
end entity control_socbridge_tb;

architecture tb of control_socbridge_tb is

  constant cycle : Time := 10 ns;
  signal clk, rst : std_logic;
  signal cu_to_sb_cmd: command_t;
  signal cu_to_sb_address: std_logic_vector(31 downto 0);
  signal cmd_size : positive;
  signal ext_socbridge_in  :  ext_socbridge_in_t := (
    payload => (others => '0'),
    control => (others => '0')
  );
  signal ext_socbridge_out :  ext_socbridge_out_t;
  signal int_socbridge_out  :  int_socbridge_out_t;
  signal int_socbridge_in :  int_socbridge_in_t := (
    payload => (others => '0'),
    write_enable_out => '0',
    is_full_in => '0'
  );
  signal ext_control_input: ext_control_unit_in_t := (
    driver_id => (others => '0'),
    address => (others => '0'),
    seq_mem_access_count => 0,
    cmd => x"00"
  );
  signal int_control_input: int_control_unit_in_t := (active_driver => (others => '0'));
  signal ext_control_output: ext_control_unit_out_t;
  signal int_control_output: int_control_unit_out_t;

  signal driver_to_control: driver_to_control_t;
  signal control_to_driver: control_to_driver_t;
begin

  socbridge_inst: entity socbridge.socbridge_driver
    port map(
      clk      => clk,
      rst      => rst,
      ctrl_in  => control_to_driver,
      ctrl_out => driver_to_control, 
      ext_in   => ext_socbridge_in,
      ext_out  => ext_socbridge_out,
      int_in   => int_socbridge_in,
      int_out  => int_socbridge_out
    );

  control_unit_inst: entity controller.control_unit
    port map(
      clk             => clk,
      rst             => rst,
      ext_control_in  => ext_control_input,
      ext_control_out => ext_control_output,
      int_control_in  => int_control_input,
      int_control_out => int_control_output
  );
  
  control_to_driver.address <= int_control_output.address;
  control_to_driver.request <= int_control_output.driver_id(0);
  control_to_driver.instruction <= int_control_output.instruction;
  control_to_driver.seq_mem_access_count <= int_control_output.seq_mem_access_count;
  
  int_control_input.active_driver(0) <= driver_to_control.is_active;

  clock_proc: process
  begin
  for i in 0 to 50 loop
    wait for cycle / 2;
    clk <= not clk;
  end loop;
  wait;
  end process clock_proc;
  
  stimulus_proc: process
  begin
    
  end process stimulus_proc;

  monitor_proc: process
  begin
    
  end process monitor_proc;

end architecture tb;