library IEEE;
use IEEE.std_logic_1164.all;
library ganimede;
use ganimede.io_types.all;
library gan_socbridge;
use gan_socbridge.socbridge_driver_tb_pkg.all;
library controller;

entity ganimede_toplevel is
  port (
    clk               : in  std_logic;
    rst               : in  std_logic;
    manager_to_ganimede   : in  manager_to_controller_t;
    ganimede_to_manager   : out controller_to_manager_t;
    ext_to_ganimede   : in  ext_to_ganimede_t;
    ganimede_to_ext   : out ganimede_to_ext_t;
    ip_to_ganimede    : in  ip_to_ganimede_t;
    ganimede_to_ip    : out ganimede_to_ip_t
  );
end entity ganimede_toplevel;
architecture rtl of ganimede_toplevel is
  --- SIGNAL DECLERATIONS ---
  signal ext_to_drivers        : ext_to_ganimede_t;
  signal drivers_to_ext        : ganimede_to_ext_t;
  signal drivers_to_ip         : ganimede_to_ip_t;
  signal ip_to_drivers         : ip_to_ganimede_t;
  signal drivers_to_controller : drivers_to_controller_t;
  signal controller_to_drivers : controller_to_drivers_t;


  --signal gan_socbridge_WE_in : std_logic;
  --signal gan_socbridge_WE_out : std_logic;
  --signal gan_socbridge_is_full_in : std_logic;
  --signal gan_socbridge_is_full_out : std_logic;
  
  --- COMPONENT DECLERATIONS ---
  --component fifo is 
  --  generic(
  --    WIDTH : positive;
  --    DEPTH : positive
  --  );
  --  port(
  --    clk, reset, read_enable, write_enable : in std_logic;
  --    is_full, is_empty                     : out std_logic;
  --    data_in      : in std_logic_vector(WIDTH - 1 downto 0);
  --    data_out     : out std_logic_vector(WIDTH - 1 downto 0)
  --  );
  --end component;
begin
  --- CONNECT EXTERNAL SIGNALS TO INTERNAL CONNECTIONS ---
  ip_to_drivers   <= ip_to_ganimede;
  ganimede_to_ip  <= drivers_to_ip;
  ext_to_drivers  <= ext_to_ganimede;
  ganimede_to_ext <= drivers_to_ext;

  --- DRIVER INSTANTIATION ---
  socbridge_inst: entity gan_socbridge.socbridge_driver
    port map(
      clk                            => clk,
      rst                            => rst,
      controller_to_socbridge_driver => controller_to_drivers.socbridge,
      socbridge_driver_to_controller => drivers_to_controller.socbridge,
      ext_to_socbridge_driver        => ext_to_ganimede.socbridge,
      socbridge_driver_to_ext        => ganimede_to_ext.socbridge,
      ip_to_socbridge_driver         => ip_to_ganimede.socbridge,
      socbridge_driver_to_ip         => ganimede_to_ip.socbridge
    );

  controller_unit_inst: entity controller.control_unit
    port map(
      clk                            => clk,
      rst                            => rst,
      manager_to_controller              => manager_to_ganimede,
      controller_to_manager              => ganimede_to_manager,
      drivers_to_controller          => drivers_to_controller,
      controller_to_drivers          => controller_to_drivers
  );

  --- LATER WE ADD OPTIMIZATIONS HERE ---


end architecture rtl;