library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.MATH_REAL.all;
use ieee.numeric_std.all;

entity fifo_deserializer is
  generic (
    output_width : natural := 8;
    input_width  : natural := 8;
    endianess    : integer := 0  -- 0: little endian, 1: big endian
  );
  port (
    rst, clk : in std_logic;
    ready_in : in std_logic;
    ready_out : out std_logic;
    valid_in : in std_logic;
    valid_out : out std_logic;
    data_in : in std_logic_vector(input_width - 1 downto 0);
    data_out : out std_logic_vector(output_width - 1 downto 0)
  );
end entity fifo_deserializer;

architecture rtl of fifo_deserializer is

constant out_over_in : natural := output_width / input_width - 1;
type state_t is record
  count : integer;
  data : std_logic_vector(output_width - 1 downto 0);
  full_word : std_logic;
  prev_ready : std_logic;
end record state_t;
signal st : state_t;
begin

comb_proc: process(rst,clk,valid_in,ready_in,data_in,st)
begin
  if st.full_word = '1' and ready_in = '1' then
    valid_out <= '1';
  else 
    valid_out <= '0';
  end if;
  ready_out <= ready_in;
  data_out <= st.data;
end process comb_proc; 

seq_proc: process(clk, rst)
begin
  if rst = '1' then
    st.count <= 0;
    st.data <= (others => '0');
    st.full_word <= '0';
    st.prev_ready <= '0';
  elsif (rising_edge(clk)) then
    st.prev_ready <= ready_in;
    if valid_in = '1' and st.prev_ready = '1' then
      if endianess = 0 then
        st.data((out_over_in + 1 - st.count) * input_width  - 1 downto (out_over_in - st.count) * input_width) <= data_in;
      else
        st.data((st.count + 1) * input_width - 1 downto st.count * input_width) <= data_in;
      end if;
    end if;
    if st.full_word = '1' and ready_in = '1' then
      st.full_word <= '0';
    end if;
    if st.count = out_over_in and valid_in = '1' then
      st.full_word <= '1';
      st.count <= 0;
    elsif valid_in = '1' then
      st.count <= st.count + 1;
    end if;
  end if;
end process seq_proc;

end architecture rtl;