library IEEE;  
use IEEE.std_logic_1164.all;
use IEEE.MATH_REAL.all;
use IEEE.numeric_std.all;
library ganimede;
use ganimede.io_types.all;
library manager;
use manager.management_types.all;

entity management_unit_tb is
end entity management_unit_tb;

architecture tb of management_unit_tb is
  signal clk : std_logic := '0';
  signal rst : std_logic;
  
  signal manager_to_controller       : manager_to_controller_t;       
  signal controller_to_manager       : controller_to_manager_t := (ready => '0'); 
  signal socbridge_driver_to_manager : socbridge_driver_to_manager_t := (
    address => (others => '0'),
    data => (others => '0'),
    valid => '0'
  );
  signal manager_to_socbridge_driver : manager_to_socbridge_driver_t; 

  constant halfcycle: Time := 5 ns;
  constant cycle: Time := 2 * halfcycle;

  function to_string ( a: std_logic_vector) return string is
  variable b : string (1 to a'length) := (others => NUL);
  variable stri : integer := 1; 
  begin
      for i in a'range loop
          b(stri) := std_logic'image(a((i)))(2);
      stri := stri+1;
      end loop;
  return b;
  end function;

begin
  
  clock_proc: process
  begin
  for i in 0 to 50 loop
    wait for halfcycle;
    clk <= not clk;
  end loop;
  wait;
  end process clock_proc;

  management_unit_inst: entity manager.management_unit
    port map(
    clk             => clk,
    rst             => rst,
    manager_to_controller       => manager_to_controller,
    controller_to_manager       => controller_to_manager, 
    socbridge_driver_to_manager => socbridge_driver_to_manager,
    manager_to_socbridge_driver => manager_to_socbridge_driver 
    );
  
tb_proc: process
begin
  controller_to_manager.ready <= '0'; 
  rst <= '1';
  wait for cycle;
  rst <= '0';

  report "Testing write to 0x00000014";
  socbridge_driver_to_manager.data <= x"FA0FA0FA";
  socbridge_driver_to_manager.address <= x"00000014";
  socbridge_driver_to_manager.valid <= '1';
  wait for cycle;
  socbridge_driver_to_manager.valid <= '0';
  socbridge_driver_to_manager.data <= x"00000000";
  socbridge_driver_to_manager.address <= x"00000000";
  wait for halfcycle;
  assert manager_to_socbridge_driver.data = x"FA0FA0FA" report "Write to address 0x00000005 failed! expected 0xFA0FA0FA but got " & natural'image(to_integer(unsigned(manager_to_socbridge_driver.data))) severity error;

  wait for 5 * cycle;

  report "Testing submission of write instruction of 10 words to address 0x40000000";
  controller_to_manager.ready <= '1';
  socbridge_driver_to_manager.data <= x"40000000";
  socbridge_driver_to_manager.address <= x"00000004";
  socbridge_driver_to_manager.valid <= '1';
  wait for cycle;
  socbridge_driver_to_manager.data <= x"0000000A";
  socbridge_driver_to_manager.address <= x"00000008";
  socbridge_driver_to_manager.address <= x"00000000";
  socbridge_driver_to_manager.valid <= '1';
  wait for cycle;
  socbridge_driver_to_manager.valid <= '0';
  socbridge_driver_to_manager.data <= x"00000000";
  wait for cycle;
  controller_to_manager.ready <= '1';
  wait for halfcycle;
  assert manager_to_controller.address = x"40000000" report "Controller got the wrong address! Expected 0x40000000 but got " & to_string(manager_to_controller.address) severity error;
  assert manager_to_controller.cmd = "10" report "Controller got the wrong command! Expected 0b10 but got " & to_string(manager_to_controller.cmd) severity error;  
  assert manager_to_controller.seq_mem_access_count = 10 report "Controller got the wrong message size! expected 10 but got " & natural'image(manager_to_controller.seq_mem_access_count) severity error;  

  wait for 5 * cycle;
  controller_to_manager.ready <= '0'; 

  report "Testing submission of read instruction of 20 words from address 0x50000000";
  socbridge_driver_to_manager.data <= x"50000000";
  socbridge_driver_to_manager.address <= x"00000000";
  socbridge_driver_to_manager.valid <= '1';
  wait for cycle;
  socbridge_driver_to_manager.data <= x"00000014";
  socbridge_driver_to_manager.address <= x"00000008";
  socbridge_driver_to_manager.valid <= '1';
  wait for cycle;
  socbridge_driver_to_manager.valid <= '0';
  socbridge_driver_to_manager.address <= x"00000000";
  socbridge_driver_to_manager.data <= x"00000000";
  controller_to_manager.ready <= '1';
  wait for halfcycle;
  assert manager_to_controller.address = x"50000000" report "Controller got the wrong address! Expected 0x50000000 but got " & to_string(manager_to_controller.address) severity error;
  assert manager_to_controller.cmd = "01" report "Controller got the wrong command! Expected 0b01 but got " & to_string(manager_to_controller.cmd) severity error;  
  assert manager_to_controller.seq_mem_access_count = 20 report "Controller got the wrong message size! expected 20 but got " & natural'image(manager_to_controller.seq_mem_access_count) severity error;  
  wait;
end process tb_proc;
  
end architecture tb ;