library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.io_types.all;

entity ganimede is
  port (
    ext_interface_in    : in ext_interface_in_t;
    ext_interface_out   : out ext_interface_out_t
  );
end entity ganimede;
architecture rtl of ganimede is
  --- SIGNALS INTERFACING THE IP CORE
  signal int_interface_in  : int_interface_in_t;
  signal int_interface_out : int_interface_out_t;
  
  --- COMPONENT DECLERATIONS ---
  component socbridge_driver is
    port(
      ext_in  : in ext_socbridge_in_t;
      ext_out : out ext_socbridge_out_t;
      int_in  : in int_socbridge_in_t;
      int_out : out int_socbridge_out_t
    );
  end component;

begin
  


  
end architecture rtl;