library IEEE;  
use IEEE.std_logic_1164.all;
use IEEE.MATH_REAL.all;
library work;
use work.io_types.all;

entity control_unit_tb
end entity control_unit_tb;

architecture tb of control_unit_tb is

  constant cycle := 10 ns;
  signal clock := '0';
  signal finished: std_logic;


  component control_unit is
    port(
      clk, rst: in std_logic;
      control_in: in control_unit_in_t;
      control_out: out control_unit_out_t);
  end component control_unit;

begin
 
  clock <= not clock after cycle / 2 when finished /= '1';

  control_unit_inst: control_unit
    port map(
      clk => clock,
      rst => reset,

            );

stimulus_proc: process
begin
  finished <= '0';
  
  finished <= '1';
end process stimulus_proc; 

monitor_proc: process
begin
  finished <= '0';

  finished <= '1';
end process monitor_proc;

end architecture tb;