library IEEE;  
use IEEE.std_logic_1164.all;
use IEEE.MATH_REAL.all;
library work;
use work.io_types.all;

entity control_unit is
  
  port (
    clk, rst: in std_logic;
    control_in: in control_unit_in_t;
    control_out: out control_unit_out_t
  );

end entity control_unit;

architecture behave of control_unit is
  type state_t is record
    address: std_logic_vector(address_width - 1 downto 0);
    seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
    curr_driver: std_logic_vector(number_of_drivers - 1 downto 0); --one-hot encoded, 0 means disabled
    ready: std_logic;
  end record state_t;

  signal state: state_t;
  shared variable ored: std_logic;
  

begin

  comb_proc: process(control_in, state)
  begin
    ored := '0';
    ready_reduction: for i in 0 to number_of_drivers - 1 loop
      ored := ored or control_in.active_driver(i);
    end loop ready_reduction;
    control_out.driver_id <= state.curr_driver;
    control_out.address <= state.address;
    control_out.seq_mem_access_count <= state.seq_mem_access_count;        
    control_out.ready <= state.ready;
  end process comb_proc;

  sync_proc: process(clk, state)
  begin
    if rising_edge(clk) then
      if rst = '1' then
        state <= ((others => '0'), 
                  (others => '0'), 
                  (others => '0'),
                  '1');
      else
        state.ready <= not ored;
        if ored = '0' then
          state.address <= control_in.address;
          state.seq_mem_access_count <= control_in.seq_mem_access_count;
          state.curr_driver <= control_in.driver_id;
        end if;
      end if;
    end if;
  end process sync_proc;
  
end architecture behave;