library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.MATH_REAL.all;
library gan_ganimede;
use gan_ganimede.io_types.all;
library gan_socbridge;


entity socbridge_driver_tb is
end entity socbridge_driver_tb;

architecture tb of socbridge_driver_tb is
  signal clk : std_logic := '0';
  signal rst : std_logic;
  signal ext_to_socbridge_driver  :  ext_to_socbridge_driver_t;
  signal socbridge_driver_to_ext :  socbridge_driver_to_ext_t;
  signal ip_to_socbridge_driver  :  ip_to_socbridge_driver_t;
  signal socbridge_driver_to_ip :  socbridge_driver_to_ip_t;
  signal controller_to_socbridge_driver : controller_to_socbridge_driver_t;
  signal socbridge_driver_to_controller : socbridge_driver_to_controller_t;
  shared variable done : boolean := FALSE;
  
  constant CLK_PERIOD : TIME := 10 ns;
  constant MAX_CYCLE_COUNT : INTEGER := 1000000;

begin
  socbridge_driver_inst: entity gan_socbridge.socbridge_driver
   port map(
      clk => clk,
      rst => rst,
      controller_to_socbridge_driver => controller_to_socbridge_driver,
      socbridge_driver_to_controller => socbridge_driver_to_controller,
      ext_to_socbridge_driver => ext_to_socbridge_driver,
      socbridge_driver_to_ext => socbridge_driver_to_ext,
      ip_to_socbridge_driver => ip_to_socbridge_driver,
      socbridge_driver_to_ip => socbridge_driver_to_ip
  );

  ext_to_socbridge_driver.control(1) <= clk;
  real_clk_proc: process
    variable cycle_count :integer := 0;
  begin
    while (not done) and (cycle_count < MAX_CYCLE_COUNT) loop
      clk <= not clk;
      wait for CLK_PERIOD / 2;
    end loop;
    wait;
  end process real_clk_proc;

  reset_proc: process
  begin
    rst <= '1';
    wait for CLK_PERIOD * 3;
    rst <= '0';
    wait;
  end process reset_proc;
  
  command_stimulus: process
  begin
    controller_to_socbridge_driver.instruction <= NO_OP;
    controller_to_socbridge_driver.seq_mem_access_count <= 0;
    controller_to_socbridge_driver.request <= '0';
    controller_to_socbridge_driver.address <= x"00000000";
    wait until rst='0';
    for i in 100 downto 0 loop
      wait until rising_edge(clk);
    end loop;
    controller_to_socbridge_driver.instruction <= WRITE;
    controller_to_socbridge_driver.seq_mem_access_count <= 128;
    controller_to_socbridge_driver.address <= x"40000000";
    wait until rising_edge(clk);
    controller_to_socbridge_driver.request <= '1';
    wait until socbridge_driver_to_controller.is_active = '1';
    controller_to_socbridge_driver.request <= '0';
    wait until socbridge_driver_to_controller.is_active = '0';
    for i in 100 downto 0 loop
      wait until rising_edge(clk);
    end loop;
    controller_to_socbridge_driver.instruction <= READ;
    controller_to_socbridge_driver.seq_mem_access_count <= 128;
    controller_to_socbridge_driver.address <= x"40000000";
    wait until rising_edge(clk);
    controller_to_socbridge_driver.request <= '1';
    wait until socbridge_driver_to_controller.is_active = '1';
    controller_to_socbridge_driver.request <= '0';
    wait until socbridge_driver_to_controller.is_active = '0';
    done := TRUE;
    wait;
  end process command_stimulus;

  internal_stimulus: process
    variable count : integer := 1;
  begin
    ip_to_socbridge_driver.is_full_in <= '0';
    ip_to_socbridge_driver.write_enable_out <= '0';
    wait until rst = '0';
    -- stimulus goes here

    while not done loop
      wait until (rising_edge(socbridge_driver_to_ext.control(1)) or falling_edge(socbridge_driver_to_ext.control(1))) and socbridge_driver_to_ip.is_full_out = '0';
      ip_to_socbridge_driver.payload <= std_logic_vector(to_unsigned(count, 8));
      count := count + 1;
    end loop;
    wait;
  end process internal_stimulus;
end architecture tb ;