library IEEE;  
use IEEE.std_logic_1164.all;
use IEEE.MATH_REAL.all;
use IEEE.numeric_std.all;
library ganimede;
use ganimede.io_types.all;
library controller;

entity control_unit_tb is
end entity control_unit_tb;

architecture tb of control_unit_tb is

  constant cycle: Time := 10 ns;
  signal clock: std_logic := '0';
  signal reset: std_logic := '0';
  signal ext_control_input: ext_control_unit_in_t := (
                                              (others => '0'),
                                              (others => '0'),
                                              (others => '0'),
                                              x"00");
  signal int_control_input: int_control_unit_in_t := (active_driver => (others => '0'));
  signal ext_control_output: ext_control_unit_out_t;
  signal int_control_output: int_control_unit_out_t;
  signal current_driver : std_logic_vector(2 downto 0) := "000";
  shared variable word_counter: natural := 0;

begin
  
  clock_proc: process
  begin
  for i in 0 to 50 loop
    wait for cycle / 2;
    clock <= not clock;
  end loop;
  wait;
  end process clock_proc;

  control_unit_inst: entity controller.control_unit
    port map(
    clk             => clock,
    rst             => reset,
    ext_control_in  => ext_control_input,
    ext_control_out => ext_control_output,
    int_control_in  => int_control_input,
    int_control_out => int_control_output
    );

stimulus_proc: process
begin
  wait for cycle;

  ext_control_input.driver_id <= "010";
  int_control_input.active_driver <= "000";
  ext_control_input.address <= x"F0F0F0F0";
  ext_control_input.seq_mem_access_count <= "00000011";
  ext_control_input.instruction <= x"81";
  word_counter := 3;
  wait for cycle;
  current_driver <= "010";
  
  report "entering loop with word_counter" & integer'image(word_counter);
  for_loop: for i in word_counter - 1 downto 0 loop
    wait for cycle;
    report "words remaining are " & integer'image(i);
  end loop for_loop;
  
  int_control_input.active_driver <= "000";
  report "Stim process done";
  wait;
end process stimulus_proc; 

monitor_proc: process
begin

  wait for cycle;

  wait for cycle;
  assert int_control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error;
  assert int_control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
  assert int_control_output.instruction = x"81" report "Incorrect memory op from control_unit" severity error;

  wait for 5 * cycle;
  reset <= '1';

  report "Monitor process done";
  wait;
end process monitor_proc;

end architecture tb;