library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.MATH_REAL.all;
library ganimede;
use ganimede.io_types.all;

package management_types is
  constant WORD_SIZE : natural := 32;
  -- Amount to right shift addres to convert e.g 0x00000004 to 0x00000001 for 32-bit words
  constant address_shift : natural := natural(FLOOR(LOG2(real(WORD_SIZE) / real(8))));
  subtype manager_word_t is std_logic_vector(WORD_SIZE - 1 downto 0);
  constant empty_word : std_logic_vector(WORD_SIZE - 1 downto 0) := (others => '0');
  constant mem_words : natural := 64;
  type memory_t is array (0 to mem_words - 1) of manager_word_t;

  -- Index in memory array where memory read address is kept.
  -- Read is active while it is not all zero.
  constant read_address_index  : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000000";
  -- Index in memory array where memory write address is kept.
  -- Write is active while it is not all zero. Mutex with read address
  constant write_address_index : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000001";
  constant access_size         : std_logic_vector(WORD_SIZE - 1 downto 0) := x"00000002";

  -- Status register for debugging
  type manager_state_t is record
    memory : memory_t;
    data_out : manager_word_t;
  end record manager_state_t;

  -- reset value of status register
  constant manager_state_reset_val : manager_state_t := ((others => (others => '0')), x"00000000");

  type socbridge_driver_to_manager_t is record
    address : manager_word_t;
    data : manager_word_t;
    valid: std_logic;
  end record socbridge_driver_to_manager_t;

  type manager_to_socbridge_driver_t is record
    data : manager_word_t;
    valid : std_logic;
    ready : std_logic;
  end record manager_to_socbridge_driver_t;

end package;