library IEEE;  
use IEEE.std_logic_1164.all;
use IEEE.MATH_REAL.all;
use IEEE.numeric_std.all;
library gan_ganimede;
use gan_ganimede.io_types.all;
library gan_controller;

entity control_unit_tb is
end entity control_unit_tb;

architecture tb of control_unit_tb is

  constant cycle: Time := 10 ns;
  signal clock: std_logic := '0';
  signal reset: std_logic := '0';
  signal manager_to_controller: manager_to_controller_t := (
                                              (others => '0'),
                                              (others => '0'),
                                              0,
                                              "00");
  signal drivers_to_controller: drivers_to_controller_t := (socbridge => (is_active => '0'));
  signal controller_to_manager: controller_to_manager_t;
  signal controller_to_drivers: controller_to_drivers_t;
  signal current_driver : std_logic_vector(0 downto 0) := "0";
  shared variable word_counter: natural := 0;

begin
  
  clock_proc: process
  begin
  for i in 0 to 50 loop
    wait for cycle / 2;
    clock <= not clock;
  end loop;
  wait;
  end process clock_proc;

  control_unit_inst: entity gan_controller.control_unit
    port map(
    clk             => clock,
    rst             => reset,
    manager_to_controller  => manager_to_controller,
    controller_to_manager => controller_to_manager,
    drivers_to_controller => drivers_to_controller,
    controller_to_drivers => controller_to_drivers
    );

stimulus_proc: process
begin
  wait for cycle;

  manager_to_controller.driver_id <= "1";
  drivers_to_controller.socbridge.is_active <= '0';
  manager_to_controller.address <= x"F0F0F0F0";
  manager_to_controller.seq_mem_access_count <= 3;
  manager_to_controller.cmd <= "01";
  word_counter := 3;
  wait for cycle;
  current_driver <= "1";
  
  report "entering loop with word_counter" & integer'image(word_counter);
  for_loop: for i in word_counter - 1 downto 0 loop
    wait for cycle;
    report "words remaining are " & integer'image(i);
  end loop for_loop;
  
  drivers_to_controller.socbridge.is_active <= '0';
  report "Stim process done";
  wait;
end process stimulus_proc; 

monitor_proc: process
begin

  wait for cycle;

  wait for cycle;
  assert controller_to_drivers.socbridge.request = '1' report "Incorrect driver_id from control_unit" severity error;
  assert controller_to_drivers.socbridge.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
  assert controller_to_drivers.socbridge.instruction = WRITE report "Incorrect memory op from control_unit" severity error;

  wait for 5 * cycle;
  reset <= '1';

  report "Monitor process done";
  wait;
end process monitor_proc;

end architecture tb;