library IEEE; use IEEE.std_logic_1164.all; library gan_ganimede; use gan_ganimede.io_types.all; library gan_socbridge; use gan_socbridge.socbridge_driver_pkg.all; library gan_controller; library gan_manager; use gan_manager.management_types.all; library gan_buffer; entity ganimede_toplevel is port ( clk : in std_logic; rst : in std_logic; ext_to_ganimede : in ext_to_ganimede_t; ganimede_to_ext : out ganimede_to_ext_t; ip_to_ganimede : in ip_to_ganimede_t; ganimede_to_ip : out ganimede_to_ip_t ); end entity ganimede_toplevel; architecture rtl of ganimede_toplevel is --- SIGNAL DECLERATIONS --- signal drivers_to_controller : drivers_to_controller_t; signal controller_to_drivers : controller_to_drivers_t; signal manager_to_controller : manager_to_controller_t; signal controller_to_manager : controller_to_manager_t; signal socbridge_driver_to_manager : socbridge_driver_to_manager_t; signal manager_to_socbridge_driver : manager_to_socbridge_driver_t; signal socbridge_driver_to_buffer : fifo_interface_t; signal buffer_to_socbridge_driver : fifo_interface_t; signal socbridge_clk : std_logic; signal used_slots : integer; --signal gan_socbridge_WE_in : std_logic; --signal gan_socbridge_WE_out : std_logic; --signal gan_socbridge_is_full_in : std_logic; --signal gan_socbridge_is_full_out : std_logic; begin --- CONNECT EXTERNAL SIGNALS TO INTERNAL CONNECTIONS --- --- DRIVER INSTANTIATION --- socbridge_driver_inst: entity gan_socbridge.socbridge_driver port map( clk => clk, socbridge_clk => socbridge_clk, rst => rst, controller_to_socbridge_driver => controller_to_drivers.socbridge, socbridge_driver_to_controller => drivers_to_controller.socbridge, manager_to_socbridge_driver => manager_to_socbridge_driver, socbridge_driver_to_manager => socbridge_driver_to_manager, ext_to_socbridge_driver => ext_to_ganimede.socbridge, socbridge_driver_to_ext => ganimede_to_ext.socbridge, ip_to_socbridge_driver => buffer_to_socbridge_driver, socbridge_driver_to_ip => socbridge_driver_to_buffer, used_slots => used_slots ); controller_inst: entity gan_controller.control_unit port map( clk => clk, rst => rst, manager_to_controller => manager_to_controller, controller_to_manager => controller_to_manager, drivers_to_controller => drivers_to_controller, controller_to_drivers => controller_to_drivers ); manager_inst: entity gan_manager.management_unit port map( clk => clk, rst => rst, manager_to_controller => manager_to_controller, controller_to_manager => controller_to_manager, manager_to_socbridge_driver => manager_to_socbridge_driver, socbridge_driver_to_manager => socbridge_driver_to_manager ); fifo_buffer_to_ip_inst : entity gan_buffer.fifo_buffer generic map ( buffer_size => 2*1024 ) port map( in_clk => socbridge_clk, out_clk => clk, rst => rst, ready_in => ip_to_ganimede.socbridge.ready, ready_out => buffer_to_socbridge_driver.ready, valid_in => socbridge_driver_to_buffer.valid, valid_out => ganimede_to_ip.socbridge.valid, data_in => socbridge_driver_to_buffer.data, data_out => ganimede_to_ip.socbridge.data ); fifo_buffer_from_ip_inst : entity gan_buffer.fifo_buffer generic map ( buffer_size => 2*1024 ) port map( in_clk => clk, out_clk => socbridge_clk, rst => rst, ready_in => socbridge_driver_to_buffer.ready, ready_out => ganimede_to_ip.socbridge.ready, valid_in => ip_to_ganimede.socbridge.valid, valid_out => buffer_to_socbridge_driver.valid, data_in => ip_to_ganimede.socbridge.data, data_out => buffer_to_socbridge_driver.data, used_slots => used_slots ); --- LATER WE ADD OPTIMIZATIONS HERE --- end architecture rtl;