library IEEE; use IEEE.std_logic_1164.all; use IEEE.MATH_REAL.all; use ieee.numeric_std.all; library gan_manager; use gan_manager.management_types.all; library gan_ganimede; use gan_ganimede.io_types.all; entity management_unit is port ( clk, rst : in std_logic; manager_to_controller : out manager_to_controller_t; controller_to_manager : in controller_to_manager_t; socbridge_driver_to_manager : in socbridge_driver_to_manager_t; manager_to_socbridge_driver : out manager_to_socbridge_driver_t ); end entity management_unit; architecture rtl of management_unit is signal manager_state : manager_state_t; signal write_address : manager_word_t; signal read_address : manager_word_t; -- Address indexing whole words, not bytes signal word_address : natural; signal cmd : std_logic_vector(1 downto 0); function pack(word: manager_word_t) return std_logic_vector is begin return word.address & word.size & word.command & word.reserved; end function; function unpack(word: std_logic_vector) return manager_word_t is variable val : manager_word_t; begin val.address := word(31 downto 10); val.size := word(9 downto 6); val.command := word(5 downto 3); val.reserved := word(2 downto 0); return val; end function; begin read_address <= manager_state.memory(0); write_address <= manager_state.memory(1); comb_proc: process(controller_to_manager, socbridge_driver_to_manager,manager_state) variable local_word_address : natural; begin local_word_address := to_integer(shift_right(unsigned(socbridge_driver_to_manager.address), address_shift)) mod mem_words; -- Read data from manager to SoCBridge driver manager_to_socbridge_driver.ready <= '1'; manager_to_socbridge_driver.data <= pack(manager_state.memory(local_word_address)); manager_to_socbridge_driver.valid <= '1'; word_address <= local_word_address; manager_to_controller.cmd <= cmd; end process comb_proc; -- tre sorters sätt att avsluta en skrivning: -- timeout om vi villha det -- en lastbit genooom axi interface -- vi har fått all data vi begärde. seq_proc: process(clk) begin if rising_edge(clk) then if rst = '1' then manager_state <= manager_state_reset_val; else -- Write data from SoCBridge driver to address if socbridge_driver_to_manager.valid = '1' then manager_state.memory(word_address) <= unpack(socbridge_driver_to_manager.data); if socbridge_driver_to_manager.address = read_address_index or socbridge_driver_to_manager.address = write_address_index then -- CLEAR BUFFER TO IP CORE end if; -- Is the controller done executing an instruction else if controller_to_manager.done_reading = '1' then manager_state.memory(0) <= manager_word_reset_val; end if; if controller_to_manager.done_writing = '1' then manager_state.memory(1) <= manager_word_reset_val; end if; end if; -- Is there a read instruction in memory if pack(read_address) /= empty_word and controller_to_manager.ready = '1' and controller_to_manager.done_reading = '0' then manager_to_controller.address <= read_address.address & "0000000000"; manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10; cmd <= "10"; -- Is there a write instruction in memory elsif pack(write_address) /= empty_word and controller_to_manager.ready = '1' and controller_to_manager.done_writing = '0'then manager_to_controller.address <= write_address.address & "0000000000"; manager_to_controller.driver_id <= "1"; -- Only supports one driver at present manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10; cmd <= "01"; else -- No instruction present in memory, all zeroes to control unit manager_to_controller.address <= (others => '0'); manager_to_controller.driver_id <= "0"; -- Only supprts one driver at present manager_to_controller.seq_mem_access_count <= 0; cmd <= "00"; end if; end if; end if; end process seq_proc; end architecture rtl ;