library IEEE;
library work;
use work.io_types.all;

entity test is
  port (
    t : in interface_arr_t(0 to interface_arr'length - 1)
  );
end entity test;

architecture rtl of test is
  
begin
  
  proc_name: process
  begin
    
    for x in 0 to (interface_arr'length - 1) loop
      report interface_arr(x).name ;
    end loop;
  wait;
  end process proc_name;
  
  
end architecture rtl;