library IEEE;  
use IEEE.std_logic_1164.all;
use IEEE.MATH_REAL.all;
use ieee.numeric_std.all;
library work;
use work.io_types.all;

entity control_unit_tb is
end entity control_unit_tb;

architecture tb of control_unit_tb is

  constant cycle: Time := 10 ns;
  signal clock: std_logic := '0';
  signal reset: std_logic := '0';
  signal control_input: control_unit_in_t := (
                                              (others => '0'),
                                              (others => '0'),
                                              (others => '0'),
                                              "00000011");
  signal control_output: control_unit_out_t := (
                                              (others => '0'),
                                              (others => '0'),
                                              (others => '1'),
                                              '1');
  signal current_driver : std_logic_vector(2 downto 0) := "000";
  shared variable word_counter: natural := 0;

begin
  
  clock_proc: process
  begin
  for i in 0 to 50 loop
    wait for cycle / 2;
    clock <= not clock;
  end loop;
  wait;
  end process clock_proc;

  control_unit_inst: entity work.control_unit
    port map(
      clk => clock,
      rst => reset,
      control_in => control_input,
      control_out => control_output
    );

stimulus_proc: process
begin
  wait for cycle;

  control_input.driver_id <= "010";
  control_input.active_driver <= "000";
  control_input.address <= x"F0F0F0F0";
  control_input.seq_mem_access_count <= "00000111";
  word_counter := 3;
  wait for cycle;
  current_driver <= "010";
  
  report "entering loop with word_counter" & integer'image(word_counter);
  for_loop: for i in word_counter - 1 downto 0 loop
    wait for cycle;
    report "word counter is " & integer'image(word_counter);
  end loop for_loop;
  
  control_input.active_driver <= "000";
  report "Stim process done";
  wait;
end process stimulus_proc; 

monitor_proc: process
begin

  wait for cycle;

  wait for cycle;
  assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error;
  assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
  wait for 5 * cycle;
  report "Monitor process done";
  wait;
end process monitor_proc;

end architecture tb;