library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
library gan_ganimede;
use gan_ganimede.io_types.all;
library gan_socbridge;
use gan_socbridge.socbridge_driver_pkg.all;
library gan_controller;

entity ganimede_tb is
end entity ganimede_tb;

architecture tb of ganimede_tb is

  signal done : boolean := false;
  constant CLK_PERIOD                           : Time := 10 ns;
  constant SIMULATION_CYCLE_COUNT               : integer := 2000;
  signal clk, rst                               : std_logic := '0';
  signal controller_to_socbridge_driver_cmd     : instruction_command_t;
  signal controller_to_socbridge_driver_address : std_logic_vector(31 downto 0);
  signal cmd_size                               : positive;
  signal ext_to_ganimede                : ext_to_ganimede_t := (socbridge => (
    payload => (others => '0'),
    control => (others => '0')
  ));
  signal ganimede_to_ext : ganimede_to_ext_t;
  signal ganimede_to_ip  : ganimede_to_ip_t;
  signal ganimede_to_manager : controller_to_manager_t;
  signal manager_to_ganimede : manager_to_controller_t := (
    driver_id => (others => '0'),
    address => (others => '0'),
    seq_mem_access_count => 0,
    cmd => (others => '0')
  );
  signal ip_to_ganimede : ip_to_ganimede_t := (socbridge => (
    payload => (others => '0'),
    write_enable_out => '0',
    is_full_in => '0'
  ));
  signal manager_to_controller: manager_to_controller_t := (
    driver_id => (others => '0'),
    address => (others => '0'),
    seq_mem_access_count => 0,
    cmd => "00"
  );
  signal drivers_to_controller: drivers_to_controller_t := (socbridge => (is_active => '0'));
  signal controller_to_manager: controller_to_manager_t;
  signal controller_to_drivers: controller_to_drivers_t;


begin
  ganimede_inst: entity gan_ganimede.ganimede_toplevel
    port map(
      clk                    => clk,
      rst                    => rst,
      manager_to_ganimede        => manager_to_ganimede,
      ganimede_to_manager        => ganimede_to_manager,
      ext_to_ganimede        => ext_to_ganimede,
      ganimede_to_ext        => ganimede_to_ext,
      ip_to_ganimede         => ip_to_ganimede,
      ganimede_to_ip         => ganimede_to_ip
    );
  
  ext_to_ganimede.socbridge.control(1) <= clk;
  real_clk_proc: process
    variable cycle_count :integer := 0;
  begin
    while (not done) and (cycle_count < MAX_CYCLE_COUNT) loop
      clk <= not clk;
      wait for CLK_PERIOD / 2;
    end loop;
    wait;
  end process real_clk_proc;
  
  stimulus_proc: process
  begin
    report "Starting Simulation Stimulus!";
    done <= false;
    rst <= '1';
    wait for 3 * CLK_PERIOD;
    report "Reset grace period ended, starting stimulus...";
    rst <= '0';

    report "Test finished, ending simultaion...";
    done <= true;
    wait;
  end process stimulus_proc;

  internal_stimulus: process
    variable input : positive := 1;
  begin
    ip_to_ganimede.socbridge.is_full_in <= '0';
    ip_to_ganimede.socbridge.write_enable_out <= '0';
    wait for 3 * CLK_PERIOD;
    -- stimulus goes here
    ip_to_ganimede.socbridge.write_enable_out <= '1';
    ip_to_ganimede.socbridge.payload <= std_logic_vector(to_unsigned(input, ip_to_ganimede.socbridge.payload'length));
    input := input + 1 mod 256;
    wait until rising_edge(clk) and ganimede_to_ip.socbridge.is_full_out = '0';
    wait until falling_edge(clk);
    for x in 0 to 1000 loop
      ip_to_ganimede.socbridge.payload <= std_logic_vector(to_unsigned(input, ip_to_ganimede.socbridge.payload'length));
      input := input + 1 mod 256;
      wait until rising_edge(clk) and ganimede_to_ip.socbridge.is_full_out = '0';
      wait until falling_edge(clk);
    end loop;
    wait;
  end process internal_stimulus;

end architecture tb;