87 lines
2.6 KiB
VHDL
87 lines
2.6 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.MATH_REAL.all;
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library gan_ganimede;
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use gan_ganimede.io_types.all;
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entity control_unit is
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port (
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clk, rst : in std_logic;
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manager_to_controller : in manager_to_controller_t;
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controller_to_manager : out controller_to_manager_t;
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drivers_to_controller : in drivers_to_controller_t;
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controller_to_drivers : out controller_to_drivers_t
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);
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end entity control_unit;
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architecture behave of control_unit is
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type state_t is record
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address: std_logic_vector(address_width - 1 downto 0);
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seq_mem_access_count: integer;
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curr_driver: std_logic;
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ready: std_logic;
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instruction: instruction_command_t;
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end record state_t;
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signal state: state_t;
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shared variable ored: std_logic;
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begin
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comb_proc: process(manager_to_controller, drivers_to_controller, state)
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begin
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ored := '0';
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ready_reduction: for i in 0 to number_of_drivers - 1 loop
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ored := ored or drivers_to_controller.socbridge.is_active;
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end loop ready_reduction;
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controller_to_drivers.socbridge.request <= state.curr_driver;
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controller_to_drivers.socbridge.address <= state.address;
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controller_to_drivers.socbridge.seq_mem_access_count <= state.seq_mem_access_count;
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controller_to_manager.ready <= state.ready;
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controller_to_drivers.socbridge.instruction <= state.instruction;
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end process comb_proc;
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sync_proc: process(clk, state)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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state <= ((others => '0'),
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0,
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'0',
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'1',
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NO_OP);
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else
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-- Make sure to tell the management unit instruction is done
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if ored = '0' and state.ready = '0' then
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controller_to_manager.done <= '1';
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state.ready <= '1';
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else
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controller_to_manager.done <= '0';
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end if;
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if ored = '0' then
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state.address <= manager_to_controller.address;
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state.seq_mem_access_count <= manager_to_controller.seq_mem_access_count;
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state.curr_driver <= manager_to_controller.driver_id(0);
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if manager_to_controller.cmd = "01" then
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state.instruction <= WRITE;
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elsif manager_to_controller.cmd = "10" then
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state.instruction <= READ;
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else
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state.instruction <= NO_OP;
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end if;
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else
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state <= ((others => '0'),
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0,
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'0',
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'1',
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NO_OP);
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end if;
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end if;
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end if;
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end process sync_proc;
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end architecture behave;
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