458 lines
17 KiB
VHDL
458 lines
17 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.NUMERIC_STD.all;
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library ganimede;
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use ganimede.io_types.all;
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library gan_socbridge;
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use gan_socbridge.socbridge_driver_tb_pkg.all;
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entity socbridge_driver is
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generic(
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MAX_PKT_SIZE : integer range 1 to 128 := 32
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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controller_to_socbridge_driver : in controller_to_socbridge_driver_t;
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socbridge_driver_to_controller : out socbridge_driver_to_controller_t;
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ext_to_socbridge_driver : in ext_to_socbridge_driver_t;
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socbridge_driver_to_ext : out socbridge_driver_to_ext_t;
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ip_to_socbridge_driver : in ip_to_socbridge_driver_t;
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socbridge_driver_to_ip : out socbridge_driver_to_ip_t
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);
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end entity socbridge_driver;
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architecture rtl of socbridge_driver is
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signal next_parity_out : std_logic;
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signal ext_to_socbridge_driver_rec : ext_protocol_t;
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shared variable socbridge_driver_to_ext_data_cmd : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
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shared variable next_rx_transaction : transaction_t;
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shared variable next_tx_transaction : transaction_t;
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signal test : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
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signal next_tx_data_size, next_rx_data_size : integer;
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signal next_rx_state : rx_state_t;
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signal next_tx_state : tx_state_t;
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signal curr_cmd_bits : std_logic_vector(4 downto 0);
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signal st : state_rec_t;
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--- TRANSLATOR ---
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signal trans_st : translator_state_rec_t;
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signal trans_next_state : translator_state_t;
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--- FSM COMMUNICATION ---
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signal tx_sent_response, rx_received_response : std_logic;
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--- MANAGEMENT COMMUNICATION ---
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signal mgnt_valid_in, mgnt_valid_out, mgnt_ready_out : std_logic;
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begin
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--- DEBUG GLOBAL BINDINGS ---
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-- synthesis translate_off
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G_next_parity_out <= next_parity_out;
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G_ext_to_socbridge_driver_rec <= ext_to_socbridge_driver_rec;
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G_socbridge_driver_to_ext_data_cmd <=test;
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G_curr_command_bits <= curr_cmd_bits;
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G_st <= st;
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G_trans_st <= trans_st;
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-- synthesis translate_on
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ext_to_socbridge_driver_rec.data <= ext_to_socbridge_driver.payload;
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ext_to_socbridge_driver_rec.clk <= ext_to_socbridge_driver.control(1);
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ext_to_socbridge_driver_rec.parity <= ext_to_socbridge_driver.control(0);
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comb_proc: process(ext_to_socbridge_driver, ip_to_socbridge_driver,
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st, controller_to_socbridge_driver, trans_st,
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tx_sent_response, rx_received_response)
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variable curr_response_bits : std_logic_vector(4 downto 0);
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begin
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-- Helpful Bindings --
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next_rx_data_size <= 2 ** to_integer(unsigned(ext_to_socbridge_driver.payload(2 downto 0)));
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curr_response_bits := ext_to_socbridge_driver.payload(7 downto 3);
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-- Set helper var to current transaction seen at the input.
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next_rx_transaction := NO_OP;
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if curr_response_bits = "10000" then
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next_rx_transaction := WRITE_ADD;
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elsif curr_response_bits = "10100" then
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next_rx_transaction := WRITE;
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elsif curr_response_bits = "11000" then
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next_rx_transaction := READ_ADD;
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elsif curr_response_bits = "11100" then
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next_rx_transaction := READ;
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elsif curr_response_bits = "01001" then
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next_rx_transaction := P_ERR;
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elsif curr_response_bits = "00101" or curr_response_bits = "00001" then
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next_rx_transaction := WRITE_ACK;
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elsif curr_response_bits = "01100" or curr_response_bits = "01000" then
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next_rx_transaction := READ_RESPONSE;
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end if;
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-- Outputs --
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socbridge_driver_to_ext <= create_io_type_out_from_ext_protocol(st.socbridge_driver_to_ext_reg);
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if trans_st.curr_state = IDLE then
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socbridge_driver_to_controller.is_active <= '0';
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else
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socbridge_driver_to_controller.is_active <= '1';
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end if;
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--- Next State Assignments ---
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--- ### TX NEXT STATE ASSIGNMENTS ### ---
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case st.curr_tx_state is
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when IDLE =>
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if next_tx_transaction /= NO_OP then
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next_tx_state <= TX_HEADER;
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else
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next_tx_state <= IDLE;
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end if;
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when TX_HEADER =>
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-- Commands
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if st.curr_tx_transaction = WRITE_ADD or st.curr_tx_transaction = READ_ADD then
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next_tx_state <= ADDR1;
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elsif st.curr_tx_transaction = WRITE then
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next_tx_state <= TX_W_BODY;
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elsif st.curr_tx_transaction = READ then
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next_tx_state <= TX_AWAIT;
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-- Responses
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elsif st.curr_tx_transaction = READ_RESPONSE then
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next_tx_state <= TX_R_BODY;
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else
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next_tx_state <= IDLE;
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end if;
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when TX_R_BODY =>
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if st.tx_stage = 0 then
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next_tx_state <= IDLE;
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else
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next_tx_state <= TX_R_BODY;
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end if;
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when ADDR1 =>
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next_tx_state <= ADDR2;
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when ADDR2 =>
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next_tx_state <= ADDR3;
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when ADDR3 =>
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next_tx_state <= ADDR4;
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when ADDR4 =>
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if st.curr_tx_transaction = READ_ADD then
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next_tx_state <= TX_AWAIT;
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elsif st.curr_tx_transaction = WRITE_ADD then
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next_tx_state <= TX_W_BODY;
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else
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next_tx_state <= IDLE;
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end if;
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when TX_W_BODY =>
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if st.tx_stage = 0 then
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next_tx_state <= TX_AWAIT;
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else
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next_tx_state <= TX_W_BODY;
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end if;
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when TX_AWAIT =>
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-- Wait for RX FSM to get a response
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if (st.curr_tx_transaction = WRITE_ADD or st.curr_tx_transaction = WRITE)
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and st.curr_rx_transaction = WRITE_ACK then
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next_tx_state <= IDLE;
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elsif (st.curr_tx_transaction = READ_ADD or st.curr_tx_transaction = READ)
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and st.curr_rx_transaction = READ_RESPONSE and st.rx_stage = 0 then
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next_tx_state <= IDLE;
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else
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next_tx_state <= TX_AWAIT;
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end if;
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end case;
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--- Next State Assignment Of RX FSM ---
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case st.curr_rx_state is
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when IDLE =>
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if next_rx_transaction /= NO_OP then
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next_rx_state <= RX_HEADER;
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else
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next_rx_state <= IDLE;
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end if;
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when RX_HEADER =>
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-- Commands
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if st.curr_rx_transaction = WRITE_ADD or st.curr_rx_transaction = READ_ADD then
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next_rx_state <= ADDR1;
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elsif st.curr_rx_transaction = WRITE then
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next_rx_state <= RX_W_BODY;
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elsif st.curr_rx_transaction = READ then
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next_rx_state <= RX_AWAIT;
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-- Responses
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elsif st.curr_rx_transaction = READ_RESPONSE then
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next_rx_state <= RX_R_BODY;
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else
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next_rx_state <= IDLE;
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end if;
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when RX_R_BODY =>
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if st.rx_stage = 0 then
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next_rx_state <= IDLE;
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else
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next_rx_state <= RX_R_BODY;
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end if;
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when ADDR1 =>
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next_rx_state <= ADDR2;
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when ADDR2 =>
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next_rx_state <= ADDR3;
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when ADDR3 =>
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next_rx_state <= ADDR4;
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when ADDR4 =>
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if st.curr_rx_transaction = READ_ADD then
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next_rx_state <= RX_AWAIT;
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elsif st.curr_rx_transaction = WRITE_ADD then
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next_rx_state <= RX_W_BODY;
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else
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next_rx_state <= IDLE; -- Potentially superfluous safety
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end if;
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when RX_W_BODY =>
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if st.rx_stage = 0 then
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next_rx_state <= RX_AWAIT;
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else
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next_rx_state <= RX_W_BODY;
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end if;
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when RX_AWAIT =>
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-- Wait for TX FSM to send a response
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if (st.curr_rx_transaction = WRITE_ADD or st.curr_rx_transaction = WRITE)
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and st.curr_tx_transaction = WRITE_ACK then
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next_rx_state <= IDLE;
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elsif (st.curr_rx_transaction = READ_ADD or st.curr_rx_transaction = READ)
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and st.curr_tx_transaction = READ_RESPONSE and st.tx_stage = 0 then
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next_rx_state <= IDLE;
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else
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next_rx_state <= RX_AWAIT;
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end if;
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end case;
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--- Combinatorial output based on current state ---
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socbridge_driver_to_ext_data_cmd := (others => '0');
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socbridge_driver_to_ip.is_full_out <= '1';
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socbridge_driver_to_ip.write_enable_in <= '0';
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socbridge_driver_to_ip.payload <= (others => '0');
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--- ### TX_STATE BASED OUTPUT ### ---
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case st.curr_tx_state is
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when IDLE =>
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when TX_HEADER =>
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socbridge_driver_to_ext_data_cmd := get_header_bits(st.curr_tx_transaction, st.curr_rx_transaction) & get_size_bits(st.tx_data_size);
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when TX_W_BODY =>
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if st.tx_stage > 0 then
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socbridge_driver_to_ip.is_full_out <= '0';
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socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload;
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end if;
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when TX_R_BODY =>
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if st.tx_stage > 0 then
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socbridge_driver_to_ip.is_full_out <= '0';
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socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload;
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end if;
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when TX_AWAIT =>
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when ADDR1 =>
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socbridge_driver_to_ext_data_cmd := st.curr_tx_addr(31 downto 24);
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when ADDR2 =>
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socbridge_driver_to_ext_data_cmd := st.curr_tx_addr(23 downto 16);
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when ADDR3 =>
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socbridge_driver_to_ext_data_cmd := st.curr_tx_addr(15 downto 8);
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when ADDR4 =>
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socbridge_driver_to_ext_data_cmd := st.curr_tx_addr(7 downto 0);
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end case;
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--- ### RX_STATE BASED OUTPUT ### ---
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mgnt_valid_in <= '0';
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mgnt_valid_out <= '0';
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mgnt_ready_out <= '0';
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case st.curr_rx_state is
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when IDLE =>
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when RX_HEADER =>
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when RX_W_BODY =>
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-- TODO Add output signals to management unit later
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-- TODO REPLACE TWO BELOW
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socbridge_driver_to_ip.payload <= st.ext_to_socbridge_driver_reg.data;
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socbridge_driver_to_ip.write_enable_in <= '1';
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when RX_R_BODY =>
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socbridge_driver_to_ip.payload <= st.ext_to_socbridge_driver_reg.data;
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socbridge_driver_to_ip.write_enable_in <= '1';
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when RX_AWAIT =>
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if st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
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mgnt_valid_in <= '1';
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end if;
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when ADDR1 =>
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when ADDR2 =>
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when ADDR3 =>
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when ADDR4 =>
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end case;
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next_parity_out <= calc_parity(socbridge_driver_to_ext_data_cmd);
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--- TRANSLATOR ---
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--- Next state assignment
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case trans_st.curr_state is
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when IDLE =>
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if trans_st.curr_inst.request = '1' then
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trans_next_state <= SEND;
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else
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trans_next_state <= IDLE;
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end if;
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-- Wait for driver to go idle and send next instruction. Then enter AWAIT
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when SEND =>
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if st.curr_tx_state /= IDLE then
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trans_next_state <= SEND_ACCEPTED;
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else
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trans_next_state <= SEND;
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end if;
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-- Transisitonal state to decrement counter in transition between SEND and AWAIT.
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when SEND_ACCEPTED =>
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trans_next_state <= AWAIT;
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-- Wait for driver to finish current instruction, then reenter SEND
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when AWAIT =>
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if trans_st.curr_inst.seq_mem_access_count <= 0 and st.curr_tx_state = IDLE then
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trans_next_state <= IDLE;
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elsif st.curr_tx_state = IDLE then
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trans_next_state <= SEND;
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else
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trans_next_state <= AWAIT;
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end if;
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end case;
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--- NEXT TX TRANSACTION ---
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next_tx_transaction := NO_OP;
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next_tx_data_size <= 0;
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if trans_st.curr_state = IDLE and st.curr_rx_state = RX_AWAIT then
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if st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
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next_tx_transaction := WRITE_ACK;
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elsif st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD then
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next_tx_transaction := READ_RESPONSE;
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end if;
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end if;
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case trans_st.curr_state is
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when IDLE =>
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when SEND =>
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if trans_st.is_first_word = '1' then
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if trans_st.curr_inst.instruction = READ then
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next_tx_transaction := READ_ADD;
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elsif trans_st.curr_inst.instruction = WRITE then
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next_tx_transaction := WRITE_ADD;
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end if;
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else
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if trans_st.curr_inst.instruction = READ then
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next_tx_transaction := READ;
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elsif trans_st.curr_inst.instruction = WRITE then
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next_tx_transaction := WRITE;
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end if;
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end if;
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if trans_st.curr_inst.seq_mem_access_count > MAX_PKT_SIZE then
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next_tx_data_size <= MAX_PKT_SIZE;
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elsif trans_st.curr_inst.seq_mem_access_count > 0 then
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next_tx_data_size <= trans_st.curr_inst.seq_mem_access_count;
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else
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next_tx_data_size <= 0;
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end if;
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when others =>
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end case;
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end process comb_proc;
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-- Process updating internal registers based on primary clock
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seq_proc: process(ext_to_socbridge_driver_rec.clk, rst, clk)
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begin
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if(rst = '1') then
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st.ext_to_socbridge_driver_reg.data <= (others => '0');
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st.socbridge_driver_to_ext_reg.data <= (others => '0');
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st.socbridge_driver_to_ext_reg.clk <= '0';
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st.socbridge_driver_to_ext_reg.parity <= '1';
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st.curr_tx_state <= IDLE;
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st.curr_rx_state <= IDLE;
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st.tx_stage <= 0;
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st.rx_stage <= 0;
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st.curr_tx_transaction <= NO_OP;
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st.curr_rx_transaction <= NO_OP;
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st.tx_data_size <= 0;
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st.curr_tx_addr <= (others => '0');
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st.curr_rx_addr <= (others => '0');
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st.curr_write_data <= (others => '0');
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st.curr_read_data <= (others => '0');
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elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then
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st.ext_to_socbridge_driver_reg.data <= ext_to_socbridge_driver_rec.data;
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st.ext_to_socbridge_driver_reg.clk <= ext_to_socbridge_driver_rec.clk;
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st.ext_to_socbridge_driver_reg.parity <= ext_to_socbridge_driver_rec.parity;
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st.socbridge_driver_to_ext_reg.data <= socbridge_driver_to_ext_data_cmd;
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st.socbridge_driver_to_ext_reg.clk <= not st.socbridge_driver_to_ext_reg.clk;
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st.socbridge_driver_to_ext_reg.parity <= next_parity_out;
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st.curr_tx_state <= next_tx_state;
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st.curr_rx_state <= next_rx_state;
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case st.curr_tx_state is
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when IDLE =>
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st.curr_tx_transaction <= next_tx_transaction;
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st.tx_data_size <= next_tx_data_size;
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st.curr_tx_addr <= trans_st.curr_inst.address;
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if next_tx_transaction = WRITE_ADD or next_tx_transaction = WRITE
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or next_tx_transaction = READ_RESPONSE then
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st.tx_stage <= next_tx_data_size;
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else
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st.tx_stage <= 0;
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end if;
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when TX_W_BODY =>
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if st.tx_stage > 0 then
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st.tx_stage <= st.tx_stage - 1;
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end if;
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when TX_R_BODY =>
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if st.tx_stage > 0 then
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st.tx_stage <= st.tx_stage - 1;
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end if;
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when others =>
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end case;
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case st.curr_rx_state is
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when IDLE =>
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st.curr_rx_transaction <= next_rx_transaction;
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if next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE
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or next_rx_transaction = READ_RESPONSE then
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st.rx_stage <= next_rx_data_size;
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else
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st.rx_stage <= 0;
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end if;
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when RX_HEADER =>
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if st.curr_rx_transaction = READ then
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st.curr_rx_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_addr) + 4), 32));
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end if;
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when RX_R_BODY =>
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if st.rx_stage > 0 then
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st.rx_stage <= st.rx_stage - 1;
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end if;
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when RX_W_BODY =>
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if st.rx_stage > 0 then
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st.rx_stage <= st.rx_stage - 1;
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st.curr_write_data((st.rx_stage) * 8 - 1 downto (st.rx_stage - 1) * 8) <= st.ext_to_socbridge_driver_reg.data;
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end if;
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when ADDR1 =>
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st.curr_rx_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
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when ADDR2 =>
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st.curr_rx_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
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when ADDR3 =>
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st.curr_rx_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
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when ADDR4 =>
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st.curr_rx_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
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when others =>
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end case;
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end if;
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--- TRANSLATOR ---
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if(rst = '1') then
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trans_st.curr_state <= IDLE;
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trans_st.curr_inst.request <= '0';
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trans_st.curr_inst.address <= (others => '0');
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trans_st.curr_inst.seq_mem_access_count <= 0;
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trans_st.curr_inst.instruction <= NO_OP;
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trans_st.is_first_word <= '1';
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elsif(rising_edge(clk)) then
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|
trans_st.curr_state <= trans_next_state;
|
|
case trans_st.curr_state is
|
|
when IDLE =>
|
|
if controller_to_socbridge_driver.request = '1' then
|
|
trans_st.curr_inst <= controller_to_socbridge_driver;
|
|
else
|
|
end if;
|
|
trans_st.is_first_word <= '1';
|
|
when SEND =>
|
|
when SEND_ACCEPTED =>
|
|
trans_st.curr_inst.seq_mem_access_count <= trans_st.curr_inst.seq_mem_access_count - MAX_PKT_SIZE;
|
|
when AWAIT =>
|
|
if trans_st.curr_inst.seq_mem_access_count <= 0 and st.curr_tx_state = IDLE then
|
|
trans_st.curr_inst.request <= '0';
|
|
trans_st.curr_inst.address <= (others => '0');
|
|
trans_st.curr_inst.seq_mem_access_count <= 0;
|
|
trans_st.curr_inst.instruction <= NO_OP;
|
|
end if;
|
|
trans_st.is_first_word <= '0';
|
|
when others =>
|
|
end case;
|
|
end if;
|
|
end process seq_proc;
|
|
|
|
end architecture rtl;
|