636 lines
27 KiB
VHDL
636 lines
27 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.NUMERIC_STD.all;
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library gan_ganimede;
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use gan_ganimede.io_types.all;
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library gan_socbridge;
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use gan_socbridge.socbridge_driver_pkg.all;
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library gan_manager;
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use gan_manager.management_types.all;
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library grlib;
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use grlib.stdlib.all;
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entity socbridge_driver is
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generic(
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MAX_PKT_SIZE : integer range 1 to 128 := 8;
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BUFFER_SIZE : integer
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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socbridge_clk : out std_logic;
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controller_to_socbridge_driver : in controller_to_socbridge_driver_t;
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socbridge_driver_to_controller : out socbridge_driver_to_controller_t;
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manager_to_socbridge_driver : in manager_to_socbridge_driver_t;
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socbridge_driver_to_manager : out socbridge_driver_to_manager_t;
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ext_to_socbridge_driver : in ext_to_socbridge_driver_t;
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socbridge_driver_to_ext : out socbridge_driver_to_ext_t;
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ip_to_socbridge_driver : in ip_to_socbridge_driver_t;
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socbridge_driver_to_ip : out socbridge_driver_to_ip_t
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);
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end entity socbridge_driver;
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architecture rtl of socbridge_driver is
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signal next_parity_out : std_logic;
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signal ext_to_socbridge_driver_rec : ext_protocol_t;
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signal next_data_out : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
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signal next_rx_transaction : transaction_t;
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signal next_tx_transaction : transaction_t;
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signal next_tx_data_size, next_rx_data_size : integer;
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signal next_rx_state : rx_state_t;
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signal next_tx_state : tx_state_t;
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signal st : state_rec_t;
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--- TRANSLATOR ---
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signal trans_st : translator_state_t;
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signal trans_read_next_state : ctrl_inst_state_t;
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signal trans_write_next_state : ctrl_inst_state_t;
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--- FSM COMMUNICATION ---
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--- MANAGEMENT COMMUNICATION ---
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begin
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comb_proc: process(ext_to_socbridge_driver_rec, ip_to_socbridge_driver,
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controller_to_socbridge_driver, st, trans_st)
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variable curr_response_bits : std_logic_vector(4 downto 0);
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variable local_next_rx_transaction : transaction_t;
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variable local_next_tx_transaction : transaction_t;
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variable local_next_data_out : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
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begin
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-- DEFAULT VALUES
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-- Helpful Bindings --
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ext_to_socbridge_driver_rec.data <= ext_to_socbridge_driver.payload;
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ext_to_socbridge_driver_rec.clk <= ext_to_socbridge_driver.control(1);
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ext_to_socbridge_driver_rec.parity <= ext_to_socbridge_driver.control(0);
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socbridge_clk <= ext_to_socbridge_driver_rec.clk;
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socbridge_driver_to_ip.used_slots <= 0;
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next_rx_data_size <= 2 ** to_integer(unsigned(ext_to_socbridge_driver_rec.data(2 downto 0)));
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curr_response_bits := ext_to_socbridge_driver_rec.data(7 downto 3);
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-- Set helper var to current transaction seen at the input.
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local_next_rx_transaction := NO_OP;
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if curr_response_bits = "10000" then
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local_next_rx_transaction := WRITE_ADD;
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elsif curr_response_bits = "10100" then
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local_next_rx_transaction := WRITE;
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elsif curr_response_bits = "11000" then
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local_next_rx_transaction := READ_ADD;
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elsif curr_response_bits = "11100" then
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local_next_rx_transaction := READ;
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elsif curr_response_bits = "01001" then
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local_next_rx_transaction := P_ERR;
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elsif curr_response_bits = "00101" or curr_response_bits = "00001" then
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local_next_rx_transaction := WRITE_ACK;
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elsif curr_response_bits = "01100" or curr_response_bits = "01000" then
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local_next_rx_transaction := READ_RESPONSE;
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end if;
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-- Outputs --
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socbridge_driver_to_ext.payload <= st.socbridge_driver_to_ext_reg.data;
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socbridge_driver_to_ext.control(0) <= st.socbridge_driver_to_ext_reg.parity;
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socbridge_driver_to_ext.control(1) <= st.socbridge_driver_to_ext_reg.clk;
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if trans_st.read.state = IDLE then
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socbridge_driver_to_controller.is_reading <= '0';
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else
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socbridge_driver_to_controller.is_reading <= '1';
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end if;
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if trans_st.write.state = IDLE then
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socbridge_driver_to_controller.is_writing <= '0';
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else
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socbridge_driver_to_controller.is_writing <= '1';
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end if;
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--- Next State Assignments ---
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--- ### TX NEXT STATE ASSIGNMENTS ### ---
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case st.tx_state is
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when IDLE =>
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if (local_next_tx_transaction = WRITE or local_next_tx_transaction = WRITE_ADD) and not st.write_in_flight then
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next_tx_state <= TX_HEADER;
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elsif (local_next_tx_transaction = READ or local_next_tx_transaction = READ_ADD) and not st.read_in_flight then
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next_tx_state <= TX_HEADER;
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elsif local_next_tx_transaction = READ_RESPONSE or local_next_tx_transaction = WRITE_ACK then
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next_tx_state <= TX_HEADER;
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else
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next_tx_state <= IDLE;
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end if;
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when TX_HEADER =>
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-- Commands
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if st.tx_transaction = WRITE_ADD or st.tx_transaction = READ_ADD then
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next_tx_state <= ADDR1;
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elsif st.tx_transaction = WRITE then
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next_tx_state <= TX_W_BODY;
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elsif st.tx_transaction = READ then
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next_tx_state <= IDLE;
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-- Responses
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elsif st.tx_transaction = READ_RESPONSE then
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next_tx_state <= TX_R_BODY;
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else
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next_tx_state <= IDLE;
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end if;
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when TX_R_BODY =>
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if st.tx_stage <= 1 then
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next_tx_state <= IDLE;
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else
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next_tx_state <= TX_R_BODY;
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end if;
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when ADDR1 =>
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next_tx_state <= ADDR2;
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when ADDR2 =>
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next_tx_state <= ADDR3;
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when ADDR3 =>
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next_tx_state <= ADDR4;
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when ADDR4 =>
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if st.tx_transaction = READ_ADD then
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next_tx_state <= IDLE;
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elsif st.tx_transaction = WRITE_ADD then
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next_tx_state <= TX_W_BODY;
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else
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next_tx_state <= IDLE;
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end if;
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when TX_W_BODY =>
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if st.tx_stage <= 1 then
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next_tx_state <= IDLE;
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else
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next_tx_state <= TX_W_BODY;
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end if;
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end case;
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--- Next State Assignment Of RX FSM ---
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case st.rx_state is
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when IDLE =>
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if local_next_rx_transaction /= NO_OP then
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next_rx_state <= RX_HEADER;
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else
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next_rx_state <= IDLE;
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end if;
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when RX_HEADER =>
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-- Commands
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if st.rx_transaction = WRITE_ADD or st.rx_transaction = READ_ADD then
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next_rx_state <= ADDR1;
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elsif st.rx_transaction = WRITE then
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next_rx_state <= RX_W_BODY;
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elsif st.rx_transaction = READ then
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next_rx_state <= RX_AWAIT;
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-- Responses
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elsif st.rx_transaction = READ_RESPONSE then
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next_rx_state <= RX_R_BODY;
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elsif local_next_rx_transaction /= NO_OP then
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next_rx_state <= RX_HEADER;
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else
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next_rx_state <= IDLE;
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end if;
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when RX_R_BODY =>
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if st.rx_stage <= 1 then
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if local_next_rx_transaction /= NO_OP then
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next_rx_state <= RX_HEADER;
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else
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next_rx_state <= IDLE;
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end if;
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else
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next_rx_state <= RX_R_BODY;
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end if;
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when ADDR1 =>
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next_rx_state <= ADDR2;
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when ADDR2 =>
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next_rx_state <= ADDR3;
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when ADDR3 =>
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next_rx_state <= ADDR4;
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when ADDR4 =>
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if st.rx_transaction = READ_ADD then
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next_rx_state <= RX_AWAIT;
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elsif st.rx_transaction = WRITE_ADD then
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next_rx_state <= RX_W_BODY;
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else
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next_rx_state <= IDLE; -- Potentially superfluous safety
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end if;
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when RX_W_BODY =>
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if st.rx_stage <= 1 then
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next_rx_state <= RX_AWAIT;
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else
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next_rx_state <= RX_W_BODY;
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end if;
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when RX_AWAIT =>
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-- Wait for TX FSM to send a response
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if (st.rx_transaction = WRITE_ADD or st.rx_transaction = WRITE)
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and st.tx_transaction = WRITE_ACK then
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next_rx_state <= IDLE;
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elsif (st.rx_transaction = READ_ADD or st.rx_transaction = READ)
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and st.tx_transaction = READ_RESPONSE and st.tx_stage = 1 then
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next_rx_state <= IDLE;
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else
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next_rx_state <= RX_AWAIT;
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end if;
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end case;
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--- Combinatorial output based on current state ---
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local_next_data_out := (others => '0');
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socbridge_driver_to_ip.ready <= '0';
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--- ### TX_STATE BASED OUTPUT ### ---
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case st.tx_state is
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when IDLE =>
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when TX_HEADER =>
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if st.tx_transaction = WRITE_ACK or st.tx_transaction = READ_RESPONSE then
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local_next_data_out := get_header_bits(st.tx_transaction, st.rx_transaction) & get_size_bits(st.rx_data_size);
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else
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local_next_data_out := get_header_bits(st.tx_transaction, st.rx_transaction) & get_size_bits(st.tx_data_size);
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end if;
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if st.tx_transaction = WRITE then
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socbridge_driver_to_ip.ready <= '1';
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end if;
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when TX_W_BODY =>
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if st.tx_stage > 1 then
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socbridge_driver_to_ip.ready <= '1';
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end if;
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if st.tx_stage > 0 then
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if ip_to_socbridge_driver.fifo.valid = '1' then
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local_next_data_out := ip_to_socbridge_driver.fifo.data;
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else
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local_next_data_out := (others => '0');
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end if;
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end if;
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when TX_R_BODY =>
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if st.tx_stage > 0 then
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local_next_data_out := st.manager_data((((st.tx_stage - 1) mod 4) + 1) * 8 - 1 downto ((((st.tx_stage - 1) mod 4) + 1) - 1) * 8);
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end if;
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when ADDR1 =>
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local_next_data_out := st.tx_addr(31 downto 24);
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when ADDR2 =>
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local_next_data_out := st.tx_addr(23 downto 16);
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when ADDR3 =>
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local_next_data_out := st.tx_addr(15 downto 8);
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when ADDR4 =>
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local_next_data_out := st.tx_addr(7 downto 0);
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if st.tx_transaction = WRITE_ADD then
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socbridge_driver_to_ip.ready <= '1';
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end if;
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end case;
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--- ### RX_STATE BASED OUTPUT ### ---
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socbridge_driver_to_manager.valid <= '0';
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socbridge_driver_to_manager.data <= st.manager_data;
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socbridge_driver_to_manager.address <= st.manager_addr;
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socbridge_driver_to_ip.valid <= '0';
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socbridge_driver_to_ip.data <= st.ext_to_socbridge_driver_reg.data;
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case st.rx_state is
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when RX_W_BODY =>
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if st.rx_stage mod 4 = 0 and st.rx_stage /= st.rx_data_size then
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socbridge_driver_to_manager.valid <= '1';
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end if;
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when RX_R_BODY =>
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socbridge_driver_to_ip.valid <= '1';
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when RX_AWAIT =>
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if st.rx_transaction = WRITE or st.rx_transaction = WRITE_ADD then
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socbridge_driver_to_manager.valid <= '1';
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end if;
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when others =>
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end case;
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next_parity_out <= calc_parity(local_next_data_out);
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--- TRANSLATOR ---
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--- Next state assignment
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case trans_st.write.state is
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when IDLE =>
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if st.rx_transaction = READ or st.rx_transaction = READ_ADD
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or st.rx_transaction = WRITE or st.rx_transaction = WRITE_ADD then
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trans_write_next_state <= IDLE;
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elsif trans_st.write.inst.request = '1' and (ip_to_socbridge_driver.fifo.used_slots >= MAX_PKT_SIZE
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or ip_to_socbridge_driver.flush = '1') then
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trans_write_next_state <= SEND;
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else
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trans_write_next_state <= IDLE;
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end if;
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-- Wait for driver to go idle and send next instruction. Then enter AWAIT
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when SEND =>
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if st.tx_transaction = WRITE or st.tx_transaction = WRITE_ADD then
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trans_write_next_state <= SEND_ACCEPTED;
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else
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trans_write_next_state <= SEND;
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end if;
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-- Transisitonal state to decrement counter in transition between SEND and AWAIT.
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when SEND_ACCEPTED =>
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trans_write_next_state <= AWAIT;
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-- Wait for driver to finish current instruction, then reenter SEND
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when AWAIT =>
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if trans_st.write.inst.access_count <= MAX_PKT_SIZE and not st.write_in_flight then
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trans_write_next_state <= IDLE;
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elsif ip_to_socbridge_driver.fifo.used_slots = 0 and ip_to_socbridge_driver.flush = '1'
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and not st.write_in_flight then
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trans_write_next_state <= IDLE;
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elsif not st.write_in_flight and (ip_to_socbridge_driver.fifo.used_slots >= MAX_PKT_SIZE
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or ip_to_socbridge_driver.flush = '1') then
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trans_write_next_state <= SEND;
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else
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trans_write_next_state <= AWAIT;
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end if;
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end case;
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case trans_st.read.state is
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when IDLE =>
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if next_rx_transaction = READ or next_rx_transaction = READ_ADD
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or next_rx_transaction = WRITE or next_rx_transaction = WRITE_ADD then
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trans_read_next_state <= IDLE;
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elsif st.rx_transaction = READ or st.rx_transaction = READ_ADD
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or st.rx_transaction = WRITE or st.rx_transaction = WRITE_ADD then
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trans_read_next_state <= IDLE;
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elsif trans_st.read.inst.request = '1' and BUFFER_SIZE - ip_to_socbridge_driver.read_fifo.used_slots > 2*MAX_PKT_SIZE then
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trans_read_next_state <= SEND;
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else
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trans_read_next_state <= IDLE;
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end if;
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-- Wait for driver to go idle and send next instruction. Then enter AWAIT
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when SEND =>
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if st.tx_transaction = READ or st.tx_transaction = READ_ADD then
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trans_read_next_state <= SEND_ACCEPTED;
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else
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trans_read_next_state <= SEND;
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end if;
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-- Transisitonal state to decrement counter in transition between SEND and AWAIT.
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when SEND_ACCEPTED =>
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trans_read_next_state <= AWAIT;
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-- Wait for driver to finish current instruction, then reenter SEND
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when AWAIT =>
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if trans_st.read.inst.access_count <= MAX_PKT_SIZE and not st.read_in_flight then
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trans_read_next_state <= IDLE;
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elsif ip_to_socbridge_driver.flush = '1'and not st.read_in_flight then
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trans_read_next_state <= IDLE;
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elsif not st.read_in_flight and BUFFER_SIZE - ip_to_socbridge_driver.read_fifo.used_slots > 2*MAX_PKT_SIZE then
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trans_read_next_state <= SEND;
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else
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trans_read_next_state <= AWAIT;
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end if;
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end case;
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--- NEXT TX TRANSACTION ---
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local_next_tx_transaction := NO_OP;
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next_tx_data_size <= 0;
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if trans_st.read.state = IDLE and trans_st.write.state = IDLE and st.rx_state = RX_AWAIT then
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if (st.rx_transaction = WRITE or st.rx_transaction = WRITE_ADD) and manager_to_socbridge_driver.ready = '1' then
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local_next_tx_transaction := WRITE_ACK;
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elsif (st.rx_transaction = READ or st.rx_transaction = READ_ADD) and manager_to_socbridge_driver.valid = '1' then
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next_tx_data_size <= st.rx_data_size;
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local_next_tx_transaction := READ_RESPONSE;
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end if;
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elsif trans_st.read.state = SEND
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and not ((st.last_sent_transaction = READ or st.last_sent_transaction = READ_ADD) and trans_st.write.state = SEND) then
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if trans_st.read.is_first_word = '1' then
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local_next_tx_transaction := READ_ADD;
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else
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local_next_tx_transaction := READ;
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end if;
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if trans_st.read.inst.access_count > MAX_PKT_SIZE then
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next_tx_data_size <= MAX_PKT_SIZE;
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elsif trans_st.read.inst.access_count > 0 then
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next_tx_data_size <= trans_st.read.inst.access_count;
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else
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next_tx_data_size <= 0;
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end if;
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elsif trans_st.write.state = SEND and not st.read_in_flight then
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if trans_st.write.is_first_word = '1' then
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local_next_tx_transaction := WRITE_ADD;
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else
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local_next_tx_transaction := WRITE;
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end if;
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if trans_st.write.inst.access_count > MAX_PKT_SIZE then
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next_tx_data_size <= MAX_PKT_SIZE;
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elsif trans_st.write.inst.access_count > 0 then
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next_tx_data_size <= trans_st.write.inst.access_count;
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else
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next_tx_data_size <= 0;
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end if;
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end if;
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next_tx_transaction <= local_next_tx_transaction;
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next_rx_transaction <= local_next_rx_transaction;
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next_data_out <= local_next_data_out;
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end process comb_proc;
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-- Process updating internal registers based on primary clock
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seq_proc: process(ext_to_socbridge_driver_rec.clk, rst, clk)
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begin
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if(rst = '1') then
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st <= st_reset_vec;
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elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then
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st.ext_to_socbridge_driver_reg.data <= ext_to_socbridge_driver_rec.data;
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-- PARITY CHECK NOT IMPLEMENTED, REMOVING
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--st.ext_to_socbridge_driver_reg.parity <= ext_to_socbridge_driver_rec.parity;
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st.socbridge_driver_to_ext_reg.data <= next_data_out;
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st.socbridge_driver_to_ext_reg.clk <= not st.socbridge_driver_to_ext_reg.clk;
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st.socbridge_driver_to_ext_reg.parity <= next_parity_out;
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st.tx_state <= next_tx_state;
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st.rx_state <= next_rx_state;
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case st.tx_state is
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when IDLE =>
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if ip_to_socbridge_driver.flush = '1' then
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|
st.last_sent_transaction <= NO_OP;
|
|
end if;
|
|
if (next_tx_transaction = WRITE or next_tx_transaction = WRITE_ADD
|
|
or next_tx_transaction = READ or next_tx_transaction = READ_ADD) then
|
|
if not st.read_in_flight or not st.write_in_flight then
|
|
st.tx_transaction <= next_tx_transaction;
|
|
st.tx_data_size <= next_tx_data_size;
|
|
else
|
|
st.tx_transaction <= NO_OP;
|
|
st.tx_data_size <= 0;
|
|
end if;
|
|
else
|
|
st.tx_transaction <= next_tx_transaction;
|
|
st.tx_data_size <= next_tx_data_size;
|
|
end if;
|
|
if next_tx_transaction = WRITE_ADD or next_tx_transaction = WRITE
|
|
or next_tx_transaction = READ_RESPONSE then
|
|
st.tx_addr <= trans_st.write.inst.address;
|
|
st.tx_stage <= next_tx_data_size;
|
|
else
|
|
st.tx_addr <= trans_st.read.inst.address;
|
|
st.tx_stage <= 0;
|
|
end if;
|
|
when TX_HEADER =>
|
|
if st.tx_transaction = WRITE or st.tx_transaction = WRITE_ADD then
|
|
st.last_sent_transaction <= st.tx_transaction;
|
|
if not (st.rx_state = RX_HEADER and st.rx_transaction = WRITE_ACK) then
|
|
st.write_in_flight <= true;
|
|
end if;
|
|
elsif st.tx_transaction = READ or st.tx_transaction = READ_ADD then
|
|
st.last_sent_transaction <= st.tx_transaction;
|
|
if not (st.rx_state = RX_HEADER and st.rx_transaction = READ_RESPONSE) then
|
|
st.read_in_flight <= true;
|
|
end if;
|
|
end if;
|
|
when TX_W_BODY =>
|
|
if st.tx_stage > 0 then
|
|
st.tx_stage <= st.tx_stage - 1;
|
|
end if;
|
|
when TX_R_BODY =>
|
|
if st.tx_stage > 0 then
|
|
st.tx_stage <= st.tx_stage - 1;
|
|
end if;
|
|
when others =>
|
|
end case;
|
|
case st.rx_state is
|
|
when IDLE =>
|
|
st.rx_transaction <= next_rx_transaction;
|
|
st.rx_data_size <= next_rx_data_size;
|
|
if next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE
|
|
or next_rx_transaction = READ_RESPONSE then
|
|
st.rx_stage <= next_rx_data_size;
|
|
else
|
|
st.rx_stage <= 0;
|
|
end if;
|
|
when RX_HEADER =>
|
|
if st.rx_transaction = WRITE_ACK then
|
|
if not (st.tx_state = TX_HEADER and (st.tx_transaction = WRITE or st.tx_transaction = WRITE_ADD)) then
|
|
st.write_in_flight <= false;
|
|
end if;
|
|
if next_rx_transaction /= NO_OP then
|
|
st.rx_transaction <= next_rx_transaction;
|
|
st.rx_data_size <= next_rx_data_size;
|
|
if next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE
|
|
or next_rx_transaction = READ_RESPONSE then
|
|
st.rx_stage <= next_rx_data_size;
|
|
else
|
|
st.rx_stage <= 0;
|
|
end if;
|
|
end if;
|
|
elsif st.rx_transaction = READ_RESPONSE then
|
|
if not (st.tx_state = TX_HEADER and (st.tx_transaction = READ or st.tx_transaction = READ_ADD)) then
|
|
st.read_in_flight <= false;
|
|
end if;
|
|
end if;
|
|
when RX_R_BODY =>
|
|
if st.rx_stage > 0 then
|
|
st.rx_stage <= st.rx_stage - 1;
|
|
end if;
|
|
if next_rx_transaction /= NO_OP and st.rx_stage <= 1 then
|
|
st.rx_transaction <= next_rx_transaction;
|
|
st.rx_data_size <= next_rx_data_size;
|
|
if next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE
|
|
or next_rx_transaction = READ_RESPONSE then
|
|
st.rx_stage <= next_rx_data_size;
|
|
else
|
|
st.rx_stage <= 0;
|
|
end if;
|
|
end if;
|
|
when RX_W_BODY =>
|
|
if st.rx_stage > 0 then
|
|
st.rx_stage <= st.rx_stage - 1;
|
|
st.manager_data((((st.rx_stage - 1) mod 4) + 1) * 8 - 1 downto ((((st.rx_stage - 1) mod 4) + 1) - 1) * 8) <= st.ext_to_socbridge_driver_reg.data;
|
|
end if;
|
|
if (st.rx_stage - 2) mod 4 = 0 and st.rx_data_size - st.rx_stage > 4 then
|
|
st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32));
|
|
end if;
|
|
when RX_AWAIT =>
|
|
st.manager_data <= manager_to_socbridge_driver.data;
|
|
if st.tx_transaction = READ_RESPONSE or st.tx_transaction = WRITE_ACK then
|
|
if (st.rx_transaction = READ or st.rx_transaction = READ_ADD) and (st.tx_stage - 2) mod 4 = 0 then
|
|
st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32));
|
|
elsif (st.rx_transaction = WRITE or st.rx_transaction = WRITE_ADD) and (st.rx_stage - 2) mod 4 = 0 then
|
|
st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32));
|
|
end if;
|
|
end if;
|
|
when ADDR1 =>
|
|
if st.rx_transaction = READ_ADD then
|
|
st.manager_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
|
|
else
|
|
st.manager_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
|
|
end if;
|
|
when ADDR2 =>
|
|
if st.rx_transaction = READ_ADD then
|
|
st.manager_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
|
|
else
|
|
st.manager_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
|
|
end if;
|
|
when ADDR3 =>
|
|
if st.rx_transaction = READ_ADD then
|
|
st.manager_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
|
|
else
|
|
st.manager_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
|
|
end if;
|
|
when ADDR4 =>
|
|
if st.rx_transaction = READ_ADD then
|
|
st.manager_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
|
|
else
|
|
st.manager_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
|
|
end if;
|
|
when others =>
|
|
end case;
|
|
end if;
|
|
|
|
--- TRANSLATOR ---
|
|
|
|
if(rst = '1') then
|
|
trans_st <= translator_reset_vec;
|
|
elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then
|
|
trans_st.read.state <= trans_read_next_state;
|
|
trans_st.write.state <= trans_write_next_state;
|
|
case trans_st.write.state is
|
|
when IDLE =>
|
|
if controller_to_socbridge_driver.request = '1' and controller_to_socbridge_driver.instruction = WRITE
|
|
and trans_st.write.inst.request = '0' then
|
|
trans_st.write.inst.request <= controller_to_socbridge_driver.request;
|
|
trans_st.write.inst.address <= controller_to_socbridge_driver.address;
|
|
trans_st.write.inst.access_count <= controller_to_socbridge_driver.seq_mem_access_count;
|
|
else
|
|
end if;
|
|
trans_st.write.is_first_word <= '1';
|
|
when SEND =>
|
|
if trans_st.write.inst.access_count mod 256 = 0 then
|
|
trans_st.write.is_first_word <= '1';
|
|
elsif st.last_sent_transaction = READ or st.last_sent_transaction = READ_ADD
|
|
or next_tx_transaction = READ or next_tx_transaction = READ_ADD then
|
|
trans_st.write.is_first_word <= '1';
|
|
else
|
|
trans_st.write.is_first_word <= '0';
|
|
end if;
|
|
when SEND_ACCEPTED =>
|
|
trans_st.write.inst.access_count <= trans_st.write.inst.access_count - MAX_PKT_SIZE;
|
|
trans_st.write.inst.address <= std_logic_vector(unsigned(trans_st.write.inst.address) + MAX_PKT_SIZE);
|
|
when AWAIT =>
|
|
if ((ip_to_socbridge_driver.fifo.used_slots = 0 and ip_to_socbridge_driver.flush = '1')
|
|
or trans_st.write.inst.access_count <= 0)
|
|
and st.tx_state = TX_W_BODY then
|
|
trans_st.write.inst <= ctrl_inst_reset_vec;
|
|
end if;
|
|
if trans_st.write.inst.access_count mod 256 = 0 then
|
|
trans_st.write.is_first_word <= '1';
|
|
elsif st.last_sent_transaction = READ or st.last_sent_transaction = READ_ADD
|
|
or next_tx_transaction = READ or next_tx_transaction = READ_ADD then
|
|
trans_st.write.is_first_word <= '1';
|
|
else
|
|
trans_st.write.is_first_word <= '0';
|
|
end if;
|
|
when others =>
|
|
end case;
|
|
case trans_st.read.state is
|
|
when IDLE =>
|
|
if controller_to_socbridge_driver.request = '1' and controller_to_socbridge_driver.instruction = READ then
|
|
trans_st.read.inst.request <= controller_to_socbridge_driver.request;
|
|
trans_st.read.inst.address <= controller_to_socbridge_driver.address;
|
|
trans_st.read.inst.access_count <= controller_to_socbridge_driver.seq_mem_access_count;
|
|
else
|
|
end if;
|
|
trans_st.read.is_first_word <= '1';
|
|
when SEND =>
|
|
if trans_st.read.inst.access_count mod 256 = 0 then
|
|
trans_st.read.is_first_word <= '1';
|
|
elsif st.last_sent_transaction = WRITE or st.last_sent_transaction = WRITE_ADD
|
|
or next_tx_transaction = WRITE or next_tx_transaction = WRITE_ADD then
|
|
trans_st.read.is_first_word <= '1';
|
|
else
|
|
trans_st.read.is_first_word <= '0';
|
|
end if;
|
|
when SEND_ACCEPTED =>
|
|
trans_st.read.inst.access_count <= trans_st.read.inst.access_count - MAX_PKT_SIZE;
|
|
trans_st.read.inst.address <= std_logic_vector(unsigned(trans_st.read.inst.address) + MAX_PKT_SIZE);
|
|
when AWAIT =>
|
|
if (ip_to_socbridge_driver.flush = '1' or trans_st.read.inst.access_count <= 0) and st.tx_state = IDLE then
|
|
trans_st.read.inst <= ctrl_inst_reset_vec;
|
|
end if;
|
|
if trans_st.read.inst.access_count mod 256 = 0 then
|
|
trans_st.read.is_first_word <= '1';
|
|
elsif st.last_sent_transaction = WRITE or st.last_sent_transaction = WRITE_ADD
|
|
or next_tx_transaction = WRITE or next_tx_transaction = WRITE_ADD then
|
|
trans_st.read.is_first_word <= '1';
|
|
else
|
|
trans_st.read.is_first_word <= '0';
|
|
end if;
|
|
when others =>
|
|
end case;
|
|
end if;
|
|
end process seq_proc;
|
|
|
|
end architecture rtl;
|