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made some progress on reformatting socbridge driver

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This commit is contained in:
Erik Örtenberg 2025-04-03 17:13:01 +02:00
parent ffa2ee768c
commit 0747cbfdc9
3 changed files with 139 additions and 152 deletions
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1
src/.gitignore vendored Normal file
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@ -0,0 +1 @@
**/grlib*/**

260
src/socbridge/socbridge_driver.vhd
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@ -29,13 +29,12 @@ architecture rtl of socbridge_driver is
signal ext_to_socbridge_driver_rec : ext_protocol_t; signal ext_to_socbridge_driver_rec : ext_protocol_t;
shared variable socbridge_driver_to_ext_data_cmd : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0); shared variable socbridge_driver_to_ext_data_cmd : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
shared variable next_rx_transaction : transaction_t; shared variable next_rx_transaction : transaction_t;
shared variable next_tx_transaction : transaction_t;
signal test : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0); signal test : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
signal next_cmd : command_t;
signal next_cmd_size : integer; signal next_cmd_size : integer;
signal next_rx_state : rx_state_t; signal next_rx_state : rx_state_t;
signal next_tx_state : tx_state_t; signal next_tx_state : tx_state_t;
signal curr_cmd_bits : std_logic_vector(4 downto 0); signal curr_cmd_bits : std_logic_vector(4 downto 0);
signal curr_response : response_t;
signal curr_response_bits : std_logic_vector(4 downto 0); signal curr_response_bits : std_logic_vector(4 downto 0);
signal st : state_rec_t; signal st : state_rec_t;
--- TRANSLATOR --- --- TRANSLATOR ---
@ -46,10 +45,8 @@ begin
-- synthesis translate_off -- synthesis translate_off
G_next_parity_out <= next_parity_out; G_next_parity_out <= next_parity_out;
G_ext_to_socbridge_driver_rec <= ext_to_socbridge_driver_rec; G_ext_to_socbridge_driver_rec <= ext_to_socbridge_driver_rec;
G_next_rx_state <= next_rx_state;
G_socbridge_driver_to_ext_data_cmd <=test; G_socbridge_driver_to_ext_data_cmd <=test;
G_curr_command_bits <= curr_cmd_bits; G_curr_command_bits <= curr_cmd_bits;
G_curr_response <= curr_response;
G_curr_response_bits <= curr_response_bits; G_curr_response_bits <= curr_response_bits;
G_st <= st; G_st <= st;
G_trans_st <= trans_st; G_trans_st <= trans_st;
@ -80,6 +77,9 @@ begin
begin begin
-- Outputs -- Outputs
socbridge_driver_to_ext <= create_io_type_out_from_ext_protocol(st.socbridge_driver_to_ext_reg); socbridge_driver_to_ext <= create_io_type_out_from_ext_protocol(st.socbridge_driver_to_ext_reg);
-- Set helper var to current transaction seen at the input.
next_rx_transaction := NO_OP;
if curr_response_bits = "10000" then if curr_response_bits = "10000" then
next_rx_transaction := WRITE_ADD; next_rx_transaction := WRITE_ADD;
elsif curr_response_bits = "10100" then elsif curr_response_bits = "10100" then
@ -94,8 +94,6 @@ begin
next_rx_transaction := WRITE_ACK; next_rx_transaction := WRITE_ACK;
elsif curr_response_bits = "01100" then elsif curr_response_bits = "01100" then
next_rx_transaction := READ_RESPONSE; next_rx_transaction := READ_RESPONSE;
else
next_rx_transaction := NO_OP;
end if; end if;
if trans_st.curr_state = IDLE then if trans_st.curr_state = IDLE then
@ -104,75 +102,20 @@ begin
socbridge_driver_to_controller.is_active <= '1'; socbridge_driver_to_controller.is_active <= '1';
end if; end if;
--- State Transition Diagram OUTDATED!! ---
--
--
--
-- +-----+
-- | |
-- V /--+
-- IDLE<-------------------+
-- / \ |
-- / \ |
-- / \ |
-- V V |
-- TX_HEADER RX_HEADER |
-- | \ / | |
-- | V V | |
-- | ADDR1 | |
-- | | | |
-- | V | |
-- | ADDR2 | |
-- | | | |
-- | V | |
-- | ADDR3 | |
-- | | | |
-- | V | |
-- | ADDR4 | |
-- | /\ | |
-- | / \ | |
-- |-+ +----| +---+ |
-- V V V | |
-- TX_BODY RX_RESPONSE---+ |
-- | | |
-- | +--+ | |
-- V V | V |
-- TX_ACK--+ RX_BODY |
-- | | |
-- | | |
-- +-----------+--------------+
--
--- Next State Assignment Of RX FSM --- --- Next State Assignment Of RX FSM ---
case st.curr_rx_state is case st.curr_rx_state is
when IDLE => when IDLE =>
if next_rx_transaction /= NO_OP then if st.curr_rx_transaction /= NO_OP then
next_rx_state <= RX_HEADER; --next_rx_state <= TX_HEADER;
else else
next_rx_state <= IDLE; next_rx_state <= IDLE;
end if; end if;
when RX_HEADER => when RX_R_BODY =>
-- The header only takes one word (cycle) to transmit. -- Here we want to stay in RX_R_BODY for the duration of a packet.
-- Continue to awaiting response directly afterwards.
if next_rx_transaction = READ_ADD or next_rx_transaction = WRITE_ADD then
next_rx_state <= ADDR1;
elsif next_rx_transaction = WRITE_ACK then
next_rx_state <= IDLE;
elsif next_rx_transaction = WRITE or next_rx_transaction = READ_RESPONSE then
next_rx_state <= RX_BODY;
elsif next_rx_transaction = WRITE_ACK then
elsif next_rx_transaction = WRITE_ACK then
elsif next_rx_transaction = WRITE_ACK then
else
-- Bogus command
next_rx_state <= IDLE;
end if;
when RX_BODY =>
-- Here we want to stay in RX_BODY for the duration of a packet.
if st.rx_stage = 0 then if st.rx_stage = 0 then
next_rx_state <= IDLE; next_rx_state <= IDLE;
else else
next_rx_state <= RX_BODY; next_rx_state <= RX_R_BODY;
end if; end if;
when ADDR1 => when ADDR1 =>
-- Transmits the entire address and returns to the appropriate -- Transmits the entire address and returns to the appropriate
@ -183,29 +126,30 @@ begin
next_rx_state <= ADDR4; next_rx_state <= ADDR4;
when ADDR4 => when ADDR4 =>
if next_rx_transaction = WRITE_ADD then if next_rx_transaction = WRITE_ADD then
next_rx_state <= RX_BODY; next_rx_state <= RX_R_BODY;
elsif next_rx_transaction = READ_ADD then elsif next_rx_transaction = READ_ADD then
next_rx_state <= TELL_TX_TO_SEND_A_READ_RESPONSE; --next_rx_state <= TELL_TX_TO_SEND_A_READ_RESPONSE;
else else
next_rx_state <= IDLE; -- Potentially superfluous safety next_rx_state <= IDLE; -- Potentially superfluous safety
end if; end if;
end case; end case;
--- Next State Assignment Of TX FSM --- --- Next State Assignments ---
--- ### TX NEXT STATE ASSIGNMENTS ### ---
case st.curr_tx_state is case st.curr_tx_state is
when IDLE => when IDLE =>
-- Do we have a command, if so enter command state. if next_tx_transaction = READ_ADD or next_tx_transaction = READ or
if st.curr_cmd = READ_ADD or st.curr_cmd = READ or next_tx_transaction = WRITE_ADD or next_tx_transaction = WRITE then
st.curr_cmd = WRITE_ADD or st.curr_cmd = WRITE then
next_tx_state <= TX_HEADER; next_tx_state <= TX_HEADER;
-- Otherwise we are ready to send a response to a read. -- Otherwise we are ready to send a response to a read.
elsif RESPONSE_READY then -- TODO define RESPONSE_READY elsif RESPONSE_READY then -- TODO define RESPONSE_READY
next_tx_state <= RESPONSE; -- IMMEDIATLY GO INTO CORRECT STATE?
--next_tx_state <= RESPONSE;
else else
next_tx_state <= IDLE; next_tx_state <= IDLE;
end if; end if;
when RESPONSE => when RESPONSE =>
-- TODO consider whether this should be moved to TX_BODY -- TODO consider whether this should be moved to TX_W_BODY
if st.tx_stage = 0 then if st.tx_stage = 0 then
next_tx_state <= IDLE; next_tx_state <= IDLE;
else else
@ -214,25 +158,17 @@ begin
when TX_HEADER => when TX_HEADER =>
-- The header only takes one word (cycle) to transmit. -- The header only takes one word (cycle) to transmit.
-- Continue to body or address directly afterwards. -- Continue to body or address directly afterwards.
if st.curr_cmd = WRITE_ADD then if st.curr_tx_transaction = WRITE_ADD then
next_tx_state <= ADDR1; next_tx_state <= ADDR1;
else else
next_tx_state <= TX_BODY; next_tx_state <= TX_W_BODY;
end if; end if;
when TX_BODY => when TX_W_BODY =>
-- Here we want to stay in TX_BODY for the duration of a packet. -- Here we want to stay in TX_W_BODY for the duration of a packet.
if st.write_stage = 0 then if st.tx_stage = 0 then
next_tx_state <= TX_ACK; next_tx_state <= TX_AWAIT;
else else
next_tx_state <= TX_BODY; next_tx_state <= TX_W_BODY;
end if;
when TX_ACK =>
-- TODO move this to rx FSM
-- Wait for write acknowledgement.
if curr_response = WRITE_ACK then
next_tx_state <= IDLE;
else
next_tx_state <= TX_ACK;
end if; end if;
when ADDR1 => when ADDR1 =>
-- Transmits the entire address and returns to the appropriate -- Transmits the entire address and returns to the appropriate
@ -242,19 +178,58 @@ begin
when ADDR3 => when ADDR3 =>
next_tx_state <= ADDR4; next_tx_state <= ADDR4;
when ADDR4 => when ADDR4 =>
if st.curr_cmd = WRITE or st.curr_cmd = WRITE_ADD then if st.curr_tx_transaction = WRITE or st.curr_tx_transaction = WRITE_ADD then
next_tx_state <= TX_BODY; next_tx_state <= TX_W_BODY;
else else
-- If it is a read instruction we wait for response. -- If it is a read instruction we wait for response.
-- TODO separate read from NO_OP and P_ERR -- TODO separate read from NO_OP and P_ERR
next_tx_state <= AWAIT_ACK; next_tx_state <= TX_AWAIT;
end if; end if;
when AWAIT_ACK => when TX_AWAIT =>
-- Wait for RX FSM to get a response -- Wait for RX FSM to get a response
if next_rx_transaction = WRITE_ACK then if st.curr_rx_transaction = WRITE_ACK or st.curr_rx_transaction = READ_RESPONSE then
next_tx_state <= IDLE; next_tx_state <= IDLE;
else else
next_tx_state <= AWAIT_ACK; next_tx_state <= TX_AWAIT;
end if;
end case;
--- ### RX NEXT STATE ASSIGNMENTS ### ---
case st.curr_rx_state is
when IDLE =>
-- Do we have a command, if so enter command state.
if next_rx_transaction = READ_ADD or next_rx_transaction = READ or
next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE then
next_rx_state <= WRITE;
-- Otherwise we are ready to send a response to a read.
elsif RESPONSE_READY then -- TODO define RESPONSE_READY
-- SHOULD WE NOT MOVE TO CORRECT RESPONSE IMMEDIATLY?
next_rx_state <= RESPONSE;
else
next_rx_state <= IDLE;
end if;
when RESPONSE =>
-- TODO consider whether this should be moved to rx_W_BODY
if st.rx_stage = 0 then
next_rx_state <= IDLE;
else
next_rx_state <= RESPONSE;
end if;
when RX_W_ACK =>
next_rx_state <= IDLE;
when RX_R_BODY =>
when ADDR1 =>
next_rx_state <= ADDR2;
when ADDR2 =>
next_rx_state <= ADDR3;
when ADDR3 =>
next_rx_state <= ADDR4;
when ADDR4 =>
if st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD then
next_rx_state <= RX_R_BODY;
else
-- If it is a read instruction we wait for response.
-- TODO separate read from NO_OP and P_ERR
--next_rx_state <= TX_AWAIT;
end if; end if;
end case; end case;
@ -264,37 +239,34 @@ begin
socbridge_driver_to_ip.is_full_out <= '1'; socbridge_driver_to_ip.is_full_out <= '1';
socbridge_driver_to_ip.write_enable_in <= '0'; socbridge_driver_to_ip.write_enable_in <= '0';
socbridge_driver_to_ip.payload <= (others => '0'); socbridge_driver_to_ip.payload <= (others => '0');
case st.curr_state is --- ### TX_STATE BASED OUTPUT ### ---
case st.curr_tx_state is
when IDLE => when IDLE =>
if st.curr_cmd = WRITE or st.curr_cmd = WRITE_ADD then if st.curr_tx_transaction = WRITE or st.curr_tx_transaction = WRITE_ADD then
socbridge_driver_to_ext_data_cmd := get_cmd_bits(st.curr_cmd) & get_size_bits(st.curr_cmd_size); socbridge_driver_to_ext_data_cmd := get_header_bits(st.curr_tx_transaction) & get_size_bits(st.curr_cmd_size);
elsif st.curr_cmd = READ or st.curr_cmd = READ_ADD then elsif st.curr_tx_transaction = READ or st.curr_tx_transaction = READ_ADD then
socbridge_driver_to_ext_data_cmd := get_cmd_bits(st.curr_cmd) & get_size_bits(st.curr_cmd_size); socbridge_driver_to_ext_data_cmd := get_header_bits(st.curr_tx_transaction) & get_size_bits(st.curr_cmd_size);
else else
end if; end if;
when TX_HEADER => when TX_HEADER =>
if st.curr_cmd = WRITE_ADD or st.curr_cmd = READ_ADD then if st.curr_tx_transaction = WRITE_ADD or st.curr_tx_transaction = READ_ADD then
socbridge_driver_to_ext_data_cmd := st.curr_addr(31 downto 24); socbridge_driver_to_ext_data_cmd := st.curr_addr(31 downto 24);
else else
socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload; socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload;
socbridge_driver_to_ip.is_full_out <= '0'; socbridge_driver_to_ip.is_full_out <= '0';
end if; end if;
when TX_BODY => when TX_W_BODY =>
if st.write_stage > 0 then if st.tx_stage > 0 then
socbridge_driver_to_ip.is_full_out <= '0'; socbridge_driver_to_ip.is_full_out <= '0';
socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload; socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload;
else else
socbridge_driver_to_ext_data_cmd := (others => '0'); socbridge_driver_to_ext_data_cmd := (others => '0');
end if; end if;
when TX_ACK => when TX_HEADER =>
when RX_HEADER => if st.curr_tx_transaction = READ_ADD then
if st.curr_cmd = READ_ADD then
socbridge_driver_to_ext_data_cmd := st.curr_addr(31 downto 24); socbridge_driver_to_ext_data_cmd := st.curr_addr(31 downto 24);
end if; end if;
when RX_RESPONSE => when TX_AWAIT =>
when RX_BODY =>
socbridge_driver_to_ip.payload <= st.ext_to_socbridge_driver_reg.data;
socbridge_driver_to_ip.write_enable_in <= '1';
when ADDR1 => when ADDR1 =>
socbridge_driver_to_ext_data_cmd := st.curr_addr(23 downto 16); socbridge_driver_to_ext_data_cmd := st.curr_addr(23 downto 16);
when ADDR2 => when ADDR2 =>
@ -302,12 +274,24 @@ begin
when ADDR3 => when ADDR3 =>
socbridge_driver_to_ext_data_cmd := st.curr_addr(7 downto 0); socbridge_driver_to_ext_data_cmd := st.curr_addr(7 downto 0);
when ADDR4 => when ADDR4 =>
if st.curr_cmd = WRITE_ADD then if st.curr_tx_transaction = WRITE_ADD then
socbridge_driver_to_ip.is_full_out <= '0'; socbridge_driver_to_ip.is_full_out <= '0';
socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload; socbridge_driver_to_ext_data_cmd := ip_to_socbridge_driver.payload;
report integer'image(to_integer(signed(socbridge_driver_to_ext_data_cmd))) & " "& integer'image(to_integer(signed(ip_to_socbridge_driver.payload))); report integer'image(to_integer(signed(socbridge_driver_to_ext_data_cmd))) & " "& integer'image(to_integer(signed(ip_to_socbridge_driver.payload)));
end if; end if;
end case; end case;
--- ### RX_STATE BASED OUTPUT ### ---
case st.curr_rx_state is
when IDLE =>
when ADDR1 =>
when ADDR2 =>
when ADDR3 =>
when ADDR4 =>
when RX_W_ACK =>
when RX_R_BODY =>
socbridge_driver_to_ip.payload <= st.ext_to_socbridge_driver_reg.data;
socbridge_driver_to_ip.write_enable_in <= '1';
end case;
next_parity_out <= calc_parity(socbridge_driver_to_ext_data_cmd); next_parity_out <= calc_parity(socbridge_driver_to_ext_data_cmd);
--- DEBUG GLOBAL BINDINGS --- --- DEBUG GLOBAL BINDINGS ---
-- synthesis translate_off -- synthesis translate_off
@ -325,7 +309,7 @@ begin
end if; end if;
-- Wait for driver to go idle and send next instruction. Then enter AWAIT -- Wait for driver to go idle and send next instruction. Then enter AWAIT
when SEND => when SEND =>
if st.curr_state /= IDLE then if st.curr_tx_state /= IDLE then
trans_next_state <= SEND_ACCEPTED; trans_next_state <= SEND_ACCEPTED;
else else
trans_next_state <= SEND; trans_next_state <= SEND;
@ -335,9 +319,9 @@ begin
trans_next_state <= AWAIT; trans_next_state <= AWAIT;
-- Wait for driver to finish current instruction, then reenter SEND -- Wait for driver to finish current instruction, then reenter SEND
when AWAIT => when AWAIT =>
if trans_st.curr_inst.seq_mem_access_count <= 0 and st.curr_state = IDLE then if trans_st.curr_inst.seq_mem_access_count <= 0 and st.curr_tx_state = IDLE then
trans_next_state <= IDLE; trans_next_state <= IDLE;
elsif st.curr_state = IDLE then elsif st.curr_tx_state = IDLE then
trans_next_state <= SEND; trans_next_state <= SEND;
else else
trans_next_state <= AWAIT; trans_next_state <= AWAIT;
@ -345,22 +329,22 @@ begin
end case; end case;
--- Combinatorial output based on state --- Combinatorial output based on state
next_cmd <= NO_OP; next_tx_transaction := NO_OP;
next_cmd_size <= 0; next_cmd_size <= 0;
case trans_st.curr_state is case trans_st.curr_state is
when IDLE => when IDLE =>
when SEND => when SEND =>
if trans_st.is_first_word = '1' then if trans_st.is_first_word = '1' then
if trans_st.curr_inst.instruction = READ then if trans_st.curr_inst.instruction = READ then
next_cmd <= READ_ADD; next_tx_transaction := READ_ADD;
elsif trans_st.curr_inst.instruction = WRITE then elsif trans_st.curr_inst.instruction = WRITE then
next_cmd <= WRITE_ADD; next_tx_transaction := WRITE_ADD;
end if; end if;
else else
if trans_st.curr_inst.instruction = READ then if trans_st.curr_inst.instruction = READ then
next_cmd <= READ; next_tx_transaction := READ;
elsif trans_st.curr_inst.instruction = WRITE then elsif trans_st.curr_inst.instruction = WRITE then
next_cmd <= WRITE; next_tx_transaction := WRITE;
end if; end if;
end if; end if;
@ -383,10 +367,11 @@ begin
st.socbridge_driver_to_ext_reg.data <= (others => '0'); st.socbridge_driver_to_ext_reg.data <= (others => '0');
st.socbridge_driver_to_ext_reg.clk <= '0'; st.socbridge_driver_to_ext_reg.clk <= '0';
st.socbridge_driver_to_ext_reg.parity <= '1'; st.socbridge_driver_to_ext_reg.parity <= '1';
st.curr_state <= IDLE; st.curr_tx_state <= IDLE;
st.write_stage <= 0; st.curr_rx_state <= IDLE;
st.tx_stage <= 0;
st.rx_stage <= 0; st.rx_stage <= 0;
st.curr_cmd <= NO_OP; st.curr_tx_transaction <= NO_OP;
st.curr_cmd_size <= 0; st.curr_cmd_size <= 0;
st.curr_addr <= (others => '0'); st.curr_addr <= (others => '0');
@ -397,33 +382,36 @@ begin
st.socbridge_driver_to_ext_reg.data <= socbridge_driver_to_ext_data_cmd; st.socbridge_driver_to_ext_reg.data <= socbridge_driver_to_ext_data_cmd;
st.socbridge_driver_to_ext_reg.clk <= not st.socbridge_driver_to_ext_reg.clk; st.socbridge_driver_to_ext_reg.clk <= not st.socbridge_driver_to_ext_reg.clk;
st.socbridge_driver_to_ext_reg.parity <= next_parity_out; st.socbridge_driver_to_ext_reg.parity <= next_parity_out;
st.curr_state <= next_state; st.curr_tx_state <= next_tx_state;
case st.curr_state is case st.curr_tx_state is
when IDLE => when IDLE =>
st.curr_cmd <= next_cmd; st.curr_tx_transaction <= next_tx_transaction;
st.curr_cmd_size <= next_cmd_size; st.curr_cmd_size <= next_cmd_size;
st.curr_addr <= trans_st.curr_inst.address; st.curr_addr <= trans_st.curr_inst.address;
if next_cmd_size > 0 then if next_cmd_size > 0 then
st.write_stage <= next_cmd_size - 1; st.tx_stage <= next_cmd_size - 1;
st.rx_stage <= next_cmd_size - 1; st.rx_stage <= next_cmd_size - 1;
end if; end if;
when TX_HEADER => when TX_HEADER =>
when TX_BODY => when TX_W_BODY =>
if st.write_stage > 0 then if st.tx_stage > 0 then
st.write_stage <= st.write_stage - 1; st.tx_stage <= st.tx_stage - 1;
end if; end if;
when TX_ACK => when others =>
st.curr_cmd <= NO_OP; end case;
case st.curr_rx_state is
when IDLE =>
st.curr_rx_transaction <= next_rx_transaction;
when RX_W_ACK =>
st.curr_tx_transaction <= NO_OP;
st.curr_cmd_size <= 0; st.curr_cmd_size <= 0;
when RX_HEADER => when RX_R_BODY =>
when RX_BODY =>
if st.rx_stage > 0 then if st.rx_stage > 0 then
st.rx_stage <= st.rx_stage - 1; st.rx_stage <= st.rx_stage - 1;
else else
st.curr_cmd <= NO_OP; st.curr_tx_transaction <= NO_OP;
st.curr_cmd_size <= 0; st.curr_cmd_size <= 0;
end if; end if;
when others => when others =>
end case; end case;
end if; end if;
@ -450,7 +438,7 @@ begin
when SEND_ACCEPTED => when SEND_ACCEPTED =>
trans_st.curr_inst.seq_mem_access_count <= trans_st.curr_inst.seq_mem_access_count - MAX_PKT_SIZE; trans_st.curr_inst.seq_mem_access_count <= trans_st.curr_inst.seq_mem_access_count - MAX_PKT_SIZE;
when AWAIT => when AWAIT =>
if trans_st.curr_inst.seq_mem_access_count <= 0 and st.curr_state = IDLE then if trans_st.curr_inst.seq_mem_access_count <= 0 and st.curr_tx_state = IDLE then
trans_st.curr_inst.request <= '0'; trans_st.curr_inst.request <= '0';
trans_st.curr_inst.address <= (others => '0'); trans_st.curr_inst.address <= (others => '0');
trans_st.curr_inst.seq_mem_access_count <= 0; trans_st.curr_inst.seq_mem_access_count <= 0;

28
src/socbridge/socbridge_driver_tb_pkg.vhd
View File

@ -13,14 +13,13 @@ package socbridge_driver_tb_pkg is
(NO_OP, WRITE_ADD, WRITE, READ_ADD, READ, P_ERR, WRITE_ACK, READ_RESPONSE); (NO_OP, WRITE_ADD, WRITE, READ_ADD, READ, P_ERR, WRITE_ACK, READ_RESPONSE);
type rx_state_t is type rx_state_t is
(IDLE, ADDR1, ADDR2, ADDR3, ADDR4, (IDLE, ADDR1, ADDR2, ADDR3, ADDR4, RX_AWAIT,
RESPONSE, READ, WRITE, PAYLOAD, RESPONSE, READ, WRITE, PAYLOAD,
RX_HEADER, RX_RESPONSE, RX_BODY); RX_W_ACK, RX_R_BODY, RX_HEADER, RX_W_BODY);
type tx_state_t is type tx_state_t is
(IDLE, ADDR1, ADDR2, ADDR3, ADDR4, (IDLE, ADDR1, ADDR2, ADDR3, ADDR4, TX_AWAIT,
RESPONSE, READ, WRITE, PAYLOAD, AWAIT_ACK, TX_HEADER, TX_W_BODY, TX_R_BODY, TX_W_ACK);
TX_HEADER, TX_BODY, TX_ACK);
--- TRANSLATOR --- --- TRANSLATOR ---
type translator_state_t is (IDLE, SEND, SEND_ACCEPTED, AWAIT); type translator_state_t is (IDLE, SEND, SEND_ACCEPTED, AWAIT);
@ -42,8 +41,7 @@ package socbridge_driver_tb_pkg is
curr_rx_state: rx_state_t; curr_rx_state: rx_state_t;
curr_tx_state: tx_state_t; curr_tx_state: tx_state_t;
ext_to_socbridge_driver_reg, socbridge_driver_to_ext_reg : ext_protocol_t; ext_to_socbridge_driver_reg, socbridge_driver_to_ext_reg : ext_protocol_t;
write_stage, rx_stage : NATURAL; tx_stage, rx_stage : NATURAL;
curr_cmd : command_t;
curr_cmd_size: integer; curr_cmd_size: integer;
curr_addr : std_logic_vector(31 downto 0); curr_addr : std_logic_vector(31 downto 0);
end record state_rec_t; end record state_rec_t;
@ -54,7 +52,7 @@ package socbridge_driver_tb_pkg is
input: ext_protocol_t input: ext_protocol_t
) return socbridge_driver_to_ext_t; ) return socbridge_driver_to_ext_t;
function to_string ( a: std_logic_vector) return string; function to_string ( a: std_logic_vector) return string;
pure function get_cmd_bits(command : command_t) return std_logic_vector; pure function get_header_bits(command : transaction_t) return std_logic_vector;
pure function get_size_bits(size : command_size_t) return std_logic_vector; pure function get_size_bits(size : command_size_t) return std_logic_vector;
pure function get_size_bits_sim(size : command_size_t) return std_logic_vector; pure function get_size_bits_sim(size : command_size_t) return std_logic_vector;
--- DEBUG GLOBAL SIGNALS --- --- DEBUG GLOBAL SIGNALS ---
@ -111,22 +109,22 @@ package body socbridge_driver_tb_pkg is
return val; return val;
end function; end function;
pure function get_cmd_bits(command : command_t) pure function get_header_bits(transaction : transaction_t)
return std_logic_vector is return std_logic_vector is
variable val : std_logic_vector(4 downto 0); variable val : std_logic_vector(4 downto 0);
begin begin
val := "11111"; val := "11111";
if command = NO_OP then if transaction = NO_OP then
val := "00000"; val := "00000";
elsif command = WRITE_ADD then elsif transaction = WRITE_ADD then
val := "10000"; val := "10000";
elsif command = WRITE then elsif transaction = WRITE then
val := "10100"; val := "10100";
elsif command = READ_ADD then elsif transaction = READ_ADD then
val := "11000"; val := "11000";
elsif command = READ then elsif transaction = READ then
val := "11100"; val := "11100";
elsif command = P_ERR then elsif transaction = P_ERR then
val := "01001"; val := "01001";
end if; end if;
return val; return val;