Multipacket socbridge works??
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1be1f1bc63
commit
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@ -13,7 +13,7 @@ use grlib.stdlib.all;
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entity socbridge_driver is
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entity socbridge_driver is
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generic(
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generic(
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MAX_PKT_SIZE : integer range 1 to 128 := 32
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MAX_PKT_SIZE : integer range 1 to 128 := 8
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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@ -184,6 +184,8 @@ begin
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-- Responses
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-- Responses
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elsif st.curr_rx_transaction = READ_RESPONSE then
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elsif st.curr_rx_transaction = READ_RESPONSE then
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next_rx_state <= RX_R_BODY;
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next_rx_state <= RX_R_BODY;
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elsif local_next_rx_transaction /= NO_OP then
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next_rx_state <= RX_HEADER;
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else
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else
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next_rx_state <= IDLE;
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next_rx_state <= IDLE;
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end if;
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end if;
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@ -510,6 +512,16 @@ begin
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if not (st.curr_tx_state = TX_HEADER and (st.curr_tx_transaction = WRITE or st.curr_tx_transaction = WRITE_ADD)) then
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if not (st.curr_tx_state = TX_HEADER and (st.curr_tx_transaction = WRITE or st.curr_tx_transaction = WRITE_ADD)) then
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st.write_in_flight <= false;
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st.write_in_flight <= false;
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end if;
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end if;
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if next_rx_transaction /= NO_OP then
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st.curr_rx_transaction <= next_rx_transaction;
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st.rx_data_size <= next_rx_data_size;
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if next_rx_transaction = WRITE_ADD or next_rx_transaction = WRITE
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or next_rx_transaction = READ_RESPONSE then
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st.rx_stage <= next_rx_data_size;
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else
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st.rx_stage <= 0;
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end if;
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end if;
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elsif st.curr_rx_transaction = READ_RESPONSE then
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elsif st.curr_rx_transaction = READ_RESPONSE then
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if not (st.curr_tx_state = TX_HEADER and (st.curr_tx_transaction = READ or st.curr_tx_transaction = READ_ADD)) then
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if not (st.curr_tx_state = TX_HEADER and (st.curr_tx_transaction = READ or st.curr_tx_transaction = READ_ADD)) then
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st.read_in_flight <= false;
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st.read_in_flight <= false;
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@ -618,7 +630,8 @@ begin
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end if;
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end if;
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if trans_st.write.curr_inst.seq_mem_access_count mod 256 = 0 then
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if trans_st.write.curr_inst.seq_mem_access_count mod 256 = 0 then
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trans_st.write.is_first_word <= '1';
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trans_st.write.is_first_word <= '1';
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elsif trans_st.read.curr_inst.instruction /= NO_OP then
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elsif st.last_sent_transaction = READ or st.last_sent_transaction = READ_ADD
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or next_tx_transaction = READ or next_tx_transaction = READ_ADD then
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trans_st.write.is_first_word <= '1';
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trans_st.write.is_first_word <= '1';
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else
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else
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trans_st.write.is_first_word <= '0';
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trans_st.write.is_first_word <= '0';
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@ -633,6 +646,14 @@ begin
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end if;
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end if;
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trans_st.read.is_first_word <= '1';
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trans_st.read.is_first_word <= '1';
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when SEND =>
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when SEND =>
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if trans_st.read.curr_inst.seq_mem_access_count mod 256 = 0 then
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trans_st.read.is_first_word <= '1';
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elsif st.last_sent_transaction = WRITE or st.last_sent_transaction = WRITE_ADD
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or next_tx_transaction = WRITE or next_tx_transaction = WRITE_ADD then
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trans_st.read.is_first_word <= '1';
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else
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trans_st.read.is_first_word <= '0';
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end if;
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when SEND_ACCEPTED =>
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when SEND_ACCEPTED =>
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trans_st.read.curr_inst.seq_mem_access_count <= trans_st.read.curr_inst.seq_mem_access_count - MAX_PKT_SIZE;
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trans_st.read.curr_inst.seq_mem_access_count <= trans_st.read.curr_inst.seq_mem_access_count - MAX_PKT_SIZE;
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trans_st.read.curr_inst.address <= std_logic_vector(unsigned(trans_st.read.curr_inst.address) + MAX_PKT_SIZE);
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trans_st.read.curr_inst.address <= std_logic_vector(unsigned(trans_st.read.curr_inst.address) + MAX_PKT_SIZE);
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@ -645,7 +666,8 @@ begin
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end if;
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end if;
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if trans_st.read.curr_inst.seq_mem_access_count mod 256 = 0 then
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if trans_st.read.curr_inst.seq_mem_access_count mod 256 = 0 then
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trans_st.read.is_first_word <= '1';
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trans_st.read.is_first_word <= '1';
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elsif trans_st.write.curr_inst.instruction /= NO_OP then
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elsif st.last_sent_transaction = WRITE or st.last_sent_transaction = WRITE_ADD
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or next_tx_transaction = WRITE or next_tx_transaction = WRITE_ADD then
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trans_st.read.is_first_word <= '1';
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trans_st.read.is_first_word <= '1';
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else
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else
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trans_st.read.is_first_word <= '0';
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trans_st.read.is_first_word <= '0';
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