kryddan/exjobb-public
1
0
Fork 0
Code Issues 2 Pull Requests Actions Packages Projects Releases Wiki Activity

Made instruction a byte instead of a bit

Browse Source
This commit is contained in:
Adam Magnusson 2025-03-04 16:33:49 +01:00 committed by Erik Örtenberg
parent 7a24dc8feb
commit 2be506209c
3 changed files with 13 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/control_unit.vhd
View File

@ -19,7 +19,8 @@ architecture behave of control_unit is
address: std_logic_vector(address_width - 1 downto 0); address: std_logic_vector(address_width - 1 downto 0);
seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
curr_driver: std_logic_vector(number_of_drivers - 1 downto 0); --one-hot encoded, 0 means disabled curr_driver: std_logic_vector(number_of_drivers - 1 downto 0); --one-hot encoded, 0 means disabled
ready, is_write: std_logic; ready: std_logic;
instruction: std_logic_vector(inst_word_width - 1 downto 0);
end record state_t; end record state_t;
signal state: state_t; signal state: state_t;
@ -38,7 +39,7 @@ begin
control_out.address <= state.address; control_out.address <= state.address;
control_out.seq_mem_access_count <= state.seq_mem_access_count; control_out.seq_mem_access_count <= state.seq_mem_access_count;
control_out.ready <= state.ready; control_out.ready <= state.ready;
control_out.is_write <= state.is_write; control_out.instruction <= state.instruction;
end process comb_proc; end process comb_proc;
sync_proc: process(clk, state) sync_proc: process(clk, state)
@ -49,14 +50,14 @@ begin
(others => '0'), (others => '0'),
(others => '0'), (others => '0'),
'1', '1',
'0'); x"00");
else else
state.ready <= not ored; state.ready <= not ored;
if ored = '0' then if ored = '0' then
state.address <= control_in.address; state.address <= control_in.address;
state.seq_mem_access_count <= control_in.seq_mem_access_count; state.seq_mem_access_count <= control_in.seq_mem_access_count;
state.curr_driver <= control_in.driver_id; state.curr_driver <= control_in.driver_id;
state.is_write <= control_in.is_write; state.instruction <= control_in.instruction;
end if; end if;
end if; end if;
end if; end if;

8
src/control_unit_tb.vhd
View File

@ -18,13 +18,13 @@ architecture tb of control_unit_tb is
(others => '0'), (others => '0'),
(others => '0'), (others => '0'),
(others => '0'), (others => '0'),
'0'); x"00");
signal control_output: control_unit_out_t := ( signal control_output: control_unit_out_t := (
(others => '0'), (others => '0'),
(others => '0'), (others => '0'),
(others => '1'), (others => '1'),
'1', '1',
'0'); x"00");
signal current_driver : std_logic_vector(2 downto 0) := "000"; signal current_driver : std_logic_vector(2 downto 0) := "000";
shared variable word_counter: natural := 0; shared variable word_counter: natural := 0;
@ -55,7 +55,7 @@ begin
control_input.active_driver <= "000"; control_input.active_driver <= "000";
control_input.address <= x"F0F0F0F0"; control_input.address <= x"F0F0F0F0";
control_input.seq_mem_access_count <= "00000011"; control_input.seq_mem_access_count <= "00000011";
control_input.is_write <= '1'; control_input.instruction <= x"81";
word_counter := 3; word_counter := 3;
wait for cycle; wait for cycle;
current_driver <= "010"; current_driver <= "010";
@ -79,7 +79,7 @@ begin
wait for cycle; wait for cycle;
assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error; assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error;
assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error; assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
assert control_output.is_write = '0' report "Incorrect memory op from control_unit" severity error; assert control_output.instruction = x"81" report "Incorrect memory op from control_unit" severity error;
wait for 5 * cycle; wait for 5 * cycle;
reset <= '1'; reset <= '1';

6
src/io_type_pkg.vhd
View File

@ -18,19 +18,21 @@ package io_types is
constant number_of_drivers: natural := 3; constant number_of_drivers: natural := 3;
constant address_width: natural := 32; constant address_width: natural := 32;
constant seq_vector_length: natural := 8; constant seq_vector_length: natural := 8;
constant inst_word_width: natural := 8;
type control_unit_out_t is record type control_unit_out_t is record
driver_id: std_logic_vector(number_of_drivers - 1 downto 0); driver_id: std_logic_vector(number_of_drivers - 1 downto 0);
address: std_logic_vector(address_width - 1 downto 0); address: std_logic_vector(address_width - 1 downto 0);
seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
ready, is_write: std_logic; ready: std_logic;
instruction: std_logic_vector(inst_word_width - 1 downto 0);
end record control_unit_out_t; end record control_unit_out_t;
type control_unit_in_t is record type control_unit_in_t is record
driver_id, active_driver: std_logic_vector(number_of_drivers - 1 downto 0); driver_id, active_driver: std_logic_vector(number_of_drivers - 1 downto 0);
address: std_logic_vector(address_width - 1 downto 0); address: std_logic_vector(address_width - 1 downto 0);
seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0); seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
is_write: std_logic; instruction: std_logic_vector(inst_word_width - 1 downto 0);
end record control_unit_in_t; end record control_unit_in_t;
--- PROTOCOL INFORMATION --- --- PROTOCOL INFORMATION ---
constant interface_inst : interface_inst_t := ( constant interface_inst : interface_inst_t := (