Standardized fifo type adn full test debugging
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parent
241fe60024
commit
6a6ebdef95
@ -54,7 +54,13 @@ begin
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'1',
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NO_OP);
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else
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state.ready <= not ored;
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-- Make sure to tell the management unit instruction is done
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if ored = '0' and state.ready = '0' then
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controller_to_manager.done <= '1';
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state.ready <= '1';
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else
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controller_to_manager.done <= '0';
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end if;
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if ored = '0' then
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state.address <= manager_to_controller.address;
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state.seq_mem_access_count <= manager_to_controller.seq_mem_access_count;
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@ -9,18 +9,13 @@ use techmap.gencomp.all;
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entity fifo_buffer is
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generic (
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data_width : natural := 8;
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buffer_size : natural := 64;
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tech : integer := nx
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tech : integer := 0
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);
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port (
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clk, rst : in std_logic;
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ready_in : in std_logic;
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ready_out : out std_logic;
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valid_in : in std_logic;
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valid_out : out std_logic;
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data_in : in std_logic_vector(data_width - 1 downto 0);
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data_out : out std_logic_vector(data_width - 1 downto 0)
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rst, in_clk, out_clk : in std_logic;
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fifo_in : in fifo_interface_t;
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fifo_out : out fifo_interface_t
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);
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end entity fifo_buffer;
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@ -28,8 +23,8 @@ architecture rtl of fifo_buffer is
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constant address_bits : natural := integer(ceil(log2(real(buffer_size))));
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signal read_pointer : std_logic_vector(address_bits - 1 downto 0);
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signal write_pointer : std_logic_vector(address_bits - 1 downto 0);
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signal data_out_signal : std_logic_vector(data_width - 1 downto 0);
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signal data_in_signal : std_logic_vector(data_width - 1 downto 0);
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signal data_out_signal : std_logic_vector(fifo_width - 1 downto 0);
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signal data_in_signal : std_logic_vector(fifo_width - 1 downto 0);
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signal write_signal : std_logic;
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signal buffer_full : std_logic;
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signal buffer_empty : std_logic;
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@ -54,25 +49,27 @@ begin
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techmap_ram_inst : entity techmap.syncram_2p
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generic map(tech => tech,
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abits => address_bits,
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dbits => data_width
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dbits => fifo_width
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)
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port map(
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rclk => clk,
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rclk => out_clk,
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renable => '1',
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raddress => read_pointer,
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dataout => data_out_signal,
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wclk => clk,
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wclk => in_clk,
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write => write_signal,
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waddress => write_pointer,
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datain => data_in_signal,
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customclk => clk,
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customclk => in_clk, --NOTE: No clue what this does but it has to be set to something
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customout => customout
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);
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data_in_signal <= fifo_in.data;
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fifo_out.data <= data_out_signal;
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comb_proc: process(write_pointer, read_pointer)
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variable write_pointer_inc : unsigned(address_bits - 1 downto 0) := unsigned(write_pointer);
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variable write_pointer_inc : unsigned(address_bits - 1 downto 0);
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begin
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ready_out <= '1';
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fifo_out.ready <= not buffer_full;
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write_pointer_inc := unsigned(write_pointer) + 1;
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customout <= "0";
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if write_pointer_inc = unsigned(read_pointer) then
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@ -88,37 +85,31 @@ begin
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end if;
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end process comb_proc;
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seq_proc: process(rst, clk)
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seq_proc: process(rst, fifo_in)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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ready_out <= '0';
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valid_out <= '0';
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if rst = '1' then
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fifo_out.valid <= '0';
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read_pointer <= (others => '0');
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write_pointer <= (others => '0');
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data_in_signal <= (others => '0');
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data_out_signal <= (others => '0');
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write_signal <= '0';
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buffer_full <= '0';
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elsif rising_edge(in_clk) then
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if fifo_in.valid = '1' and buffer_full = '0' then
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write_signal <= '1';
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write_pointer <= std_logic_vector(unsigned(write_pointer) + 1);
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else
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write_signal <= '0';
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end if;
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end if;
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if rising_edge(out_clk) and rst = '0' then
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if fifo_in.ready = '1' and buffer_empty = '0' then
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fifo_out.valid <= '1';
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read_pointer <= std_logic_vector(unsigned(read_pointer) + 1);
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write_signal <= '1';
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else
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if ready_in = '1' and buffer_empty = '0' then
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data_out <= data_out_signal;
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valid_out <= '1';
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read_pointer <= std_logic_vector(unsigned(read_pointer) + 1);
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else
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valid_out <= '0';
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data_out <= (others => '0');
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end if;
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if valid_in = '1' then
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data_in_signal <= data_in;
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write_signal <= '1';
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write_pointer <= std_logic_vector(unsigned(write_pointer) + 1);
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else
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write_signal <= '0';
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data_in_signal <= (others => '0');
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end if;
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fifo_out.valid <= '0';
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write_signal <= '0';
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end if;
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end if;
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end process seq_proc;
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end architecture rtl;
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@ -27,8 +27,9 @@ architecture rtl of ganimede_toplevel is
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signal controller_to_manager : controller_to_manager_t;
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signal socbridge_driver_to_manager : socbridge_driver_to_manager_t;
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signal manager_to_socbridge_driver : manager_to_socbridge_driver_t;
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signal socbridge_driver_to_buffer : socbridge_driver_to_ip_t;
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signal buffer_to_socbridge_driver : ip_to_socbridge_driver_t; --TODO determine where we want to declare the IP
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signal socbridge_driver_to_buffer : fifo_interface_t;
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signal buffer_to_socbridge_driver : fifo_interface_t;
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signal socbridge_clk : std_logic;
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--signal gan_socbridge_WE_in : std_logic;
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--signal gan_socbridge_WE_out : std_logic;
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@ -42,6 +43,7 @@ begin
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socbridge_driver_inst: entity gan_socbridge.socbridge_driver
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port map(
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clk => clk,
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socbridge_clk => socbridge_clk,
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rst => rst,
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controller_to_socbridge_driver => controller_to_drivers.socbridge,
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socbridge_driver_to_controller => drivers_to_controller.socbridge,
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@ -49,8 +51,8 @@ begin
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socbridge_driver_to_manager => socbridge_driver_to_manager,
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ext_to_socbridge_driver => ext_to_ganimede.socbridge,
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socbridge_driver_to_ext => ganimede_to_ext.socbridge,
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ip_to_socbridge_driver => ip_to_ganimede.socbridge,
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socbridge_driver_to_ip => ganimede_to_ip.socbridge
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ip_to_socbridge_driver => buffer_to_socbridge_driver,
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socbridge_driver_to_ip => socbridge_driver_to_buffer
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);
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controller_inst: entity gan_controller.control_unit
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@ -75,26 +77,20 @@ begin
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fifo_buffer_to_ip_inst : entity gan_buffer.fifo_buffer
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port map(
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clk => clk,
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in_clk => socbridge_clk, --TODO wrong clock
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out_clk => clk,
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rst => rst,
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ready_in => ip_to_ganimede.socbridge.ready,
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ready_out => buffer_to_socbridge_driver.ready,
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valid_in => socbridge_driver_to_buffer.valid,
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valid_out => ganimede_to_ip.socbridge.valid,
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data_in => socbridge_driver_to_buffer.payload,
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data_out => ganimede_to_ip.socbridge.payload
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fifo_in => socbridge_driver_to_buffer,
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fifo_out => ganimede_to_ip.socbridge
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);
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fifo_buffer_from_ip_inst : entity gan_buffer.fifo_buffer
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port map(
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clk => clk,
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in_clk => clk,
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out_clk => clk,
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rst => rst,
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ready_in => socbridge_driver_to_buffer.ready,
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ready_out => ganimede_to_ip.socbridge.ready,
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valid_in => ip_to_ganimede.socbridge.valid,
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valid_out => buffer_to_socbridge_driver.valid,
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data_in => ip_to_ganimede.socbridge.payload,
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data_out => buffer_to_socbridge_driver.payload
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fifo_in => ip_to_ganimede.socbridge,
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fifo_out => buffer_to_socbridge_driver
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);
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--- LATER WE ADD OPTIMIZATIONS HERE ---
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@ -8,10 +8,16 @@ package io_types is
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constant number_of_drivers : natural := 1;
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constant address_width : natural := 32;
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constant inst_word_width : natural := 2;
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constant fifo_width : natural := 8;
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--- STANDARD TYPES ---
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type instruction_command_t is (NO_OP, READ, WRITE);
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type fifo_interface_t is record
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ready, valid : std_logic;
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data : std_logic_vector(fifo_width - 1 downto 0);
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end record fifo_interface_t;
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type ext_protocol_def_t is record
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name: string (1 to 20);
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payload_width : natural;
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@ -31,7 +37,7 @@ package io_types is
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end record manager_to_controller_t;
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type controller_to_manager_t is record
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ready : std_logic;
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ready, done : std_logic;
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end record controller_to_manager_t;
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--- PROTOCOL INFORMATION ---
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@ -61,15 +67,9 @@ package io_types is
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control : STD_LOGIC_VECTOR(interface_inst.socbridge.control_width_in - 1 downto 0);
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end record socbridge_driver_to_ext_t;
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type socbridge_driver_to_ip_t is record
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payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
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ready, valid : std_logic;
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end record socbridge_driver_to_ip_t;
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subtype socbridge_driver_to_ip_t is fifo_interface_t;
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type ip_to_socbridge_driver_t is record
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payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
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ready, valid : std_logic;
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end record ip_to_socbridge_driver_t;
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subtype ip_to_socbridge_driver_t is fifo_interface_t;
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type controller_to_drivers_t is record
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socbridge : controller_to_socbridge_driver_t;
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@ -24,6 +24,7 @@ architecture rtl of management_unit is
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signal read_address : manager_word_t;
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-- Address indexing whole words, not bytes
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signal word_address : natural;
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signal cmd : std_logic_vector(1 downto 0);
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function pack(word: manager_word_t) return std_logic_vector is
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begin
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@ -41,20 +42,19 @@ architecture rtl of management_unit is
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begin
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read_address <= manager_state.memory(0);
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write_address <= manager_state.memory(1);
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comb_proc: process(controller_to_manager, socbridge_driver_to_manager,manager_state)
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variable local_word_address : natural;
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begin
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local_word_address := to_integer(shift_right(unsigned(socbridge_driver_to_manager.address and address_mask), address_shift));
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local_word_address := to_integer(shift_right(unsigned(socbridge_driver_to_manager.address), address_shift)) mod mem_words;
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-- Read data from manager to SoCBridge driver
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manager_to_socbridge_driver.ready <= '1';
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manager_to_socbridge_driver.data <= pack(manager_state.memory(local_word_address));
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manager_to_socbridge_driver.valid <= '1';
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word_address <= local_word_address;
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manager_to_controller.cmd <= cmd;
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end process comb_proc;
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-- tre sorters sätt att avsluta en skrivning:
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@ -77,24 +77,32 @@ begin
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end if;
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end if;
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-- Is the controller done executing an instruction
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if controller_to_manager.done = '1' then
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if cmd = "10" then
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manager_state.memory(0) <= manager_word_reset_val;
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elsif cmd = "01" then
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manager_state.memory(1) <= manager_word_reset_val;
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end if;
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end if;
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-- Is there a read instruction in memory
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if pack(read_address) /= empty_word and controller_to_manager.ready = '1' then
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manager_to_controller.address <= read_address.address & "0000000000";
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manager_to_controller.driver_id <= "1"; -- Only supprts one driver at present
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manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10;
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manager_to_controller.cmd <= "10";
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cmd <= "10";
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-- Is there a write instruction in memory
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elsif pack(write_address) /= empty_word and controller_to_manager.ready = '1' then
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manager_to_controller.address <= write_address.address & "0000000000";
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manager_to_controller.driver_id <= "1"; -- Only supports one driver at present
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manager_to_controller.seq_mem_access_count <= 2**to_integer(unsigned(read_address.size)) * 2**10;
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manager_to_controller.cmd <= "01";
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cmd <= "01";
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else
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-- No instruction present in memory, all zeroes to control unit
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manager_to_controller.address <= (others => '0');
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manager_to_controller.driver_id <= "0"; -- Only supprts one driver at present
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manager_to_controller.seq_mem_access_count <= 0;
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manager_to_controller.cmd <= "00";
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cmd <= "00";
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end if;
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end if;
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end if;
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@ -15,7 +15,7 @@ architecture tb of management_unit_tb is
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signal rst : std_logic;
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signal manager_to_controller : manager_to_controller_t;
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signal controller_to_manager : controller_to_manager_t := (ready => '0');
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signal controller_to_manager : controller_to_manager_t := (ready => '0', done => '0');
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signal socbridge_driver_to_manager : socbridge_driver_to_manager_t := (
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address => (others => '0'),
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data => (others => '0'),
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@ -16,6 +16,7 @@ entity socbridge_driver is
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port(
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clk : in std_logic;
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rst : in std_logic;
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socbridge_clk : out std_logic;
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controller_to_socbridge_driver : in controller_to_socbridge_driver_t;
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socbridge_driver_to_controller : out socbridge_driver_to_controller_t;
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manager_to_socbridge_driver : in manager_to_socbridge_driver_t;
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@ -48,6 +49,7 @@ begin
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ext_to_socbridge_driver_rec.data <= ext_to_socbridge_driver.payload;
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ext_to_socbridge_driver_rec.clk <= ext_to_socbridge_driver.control(1);
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ext_to_socbridge_driver_rec.parity <= ext_to_socbridge_driver.control(0);
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socbridge_clk <= ext_to_socbridge_driver_rec.clk;
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comb_proc: process(ext_to_socbridge_driver, ip_to_socbridge_driver,
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st, controller_to_socbridge_driver, trans_st,
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@ -214,7 +216,7 @@ begin
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local_next_data_out := (others => '0');
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socbridge_driver_to_ip.ready <= '0';
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socbridge_driver_to_ip.valid <= '0';
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socbridge_driver_to_ip.payload <= (others => '0');
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socbridge_driver_to_ip.data <= (others => '0');
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--- ### TX_STATE BASED OUTPUT ### ---
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case st.curr_tx_state is
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when IDLE =>
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@ -227,7 +229,7 @@ begin
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when TX_W_BODY =>
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if st.tx_stage > 0 then
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socbridge_driver_to_ip.ready <= '1';
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local_next_data_out := ip_to_socbridge_driver.payload;
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local_next_data_out := ip_to_socbridge_driver.data;
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end if;
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when TX_R_BODY =>
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if st.tx_stage > 0 then
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@ -252,7 +254,7 @@ begin
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when RX_HEADER =>
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when RX_W_BODY =>
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when RX_R_BODY =>
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socbridge_driver_to_ip.payload <= st.ext_to_socbridge_driver_reg.data;
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socbridge_driver_to_ip.data <= st.ext_to_socbridge_driver_reg.data;
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socbridge_driver_to_ip.valid <= '1';
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when RX_AWAIT =>
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if st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
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@ -99,7 +99,7 @@ begin
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while not done loop
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wait until (rising_edge(socbridge_driver_to_ext.control(1)) or falling_edge(socbridge_driver_to_ext.control(1))) and socbridge_driver_to_ip.ready = '1';
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ip_to_socbridge_driver.payload <= std_logic_vector(to_unsigned(count, 8));
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ip_to_socbridge_driver.data <= std_logic_vector(to_unsigned(count, 8));
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count := count + 1;
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end loop;
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wait;
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