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Started work on control functionality, not tested

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Adam 2025-02-25 17:11:29 +01:00 committed by Erik Örtenberg
parent 8b0ec9a856
commit 848eaf4c7a
2 changed files with 49 additions and 15 deletions
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47
src/control_unit.vhd
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@ -8,27 +8,54 @@ entity control_unit is
port (
clk, rst: in std_logic;
address_read_in, address_write_in: in control_unit_ext_t.address;
address_read_out, address_write_out: in control_unit_ext_t.address);
words_to_read_in: in std_logic_vector(control_unit_ext_t.seq_read_count);
words_to_write_in: in std_logic_vector(control_unit_ext_t.seq_write_count);
control_in: in control_unit_in_t;
control_out: out control_unit_out_t
);
end entity control_unit;
architecture behave of control_unit is
type state_t is record
address: std_logic_vector(address_width - 1 downto 0);
seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
curr_driver: std_logic_vector(number_of_drivers - 1 downto 0); --one-hot encoded, 0 means disabled
ready: std_logic
end record type_name;
signal state: state_t := (others => '0',
others => '0',
others => '0',
'1');
begin
main_proc: process(clk)
comb_proc: process(control_in, control_out, state)
variable ored: std_logic := '0';
begin
ready_reduction: for i in 0 to number_of_drivers loop
ored <= ored or control_in.active_driver(i);
end loop ready_reduction;
ready <= ored;
end process comb_proc;
sync_proc: process(clk, state)
begin
if rising_edge(clk) then
if rst = '0' then
state <= (others => '0',
others => '0',
others => '0');
else
if state.ready = '1' then
state.address <= control_in.address;
state.seq_mem_access_count <= control_in.seq_mem_access_count;
state.curr_driver <= control_in.driver_id;
end if;
control_out.driver_id <= state.curr_driver;
control_out.address <= state.address;
control_out.seq_mem_access_count <= state.seq_mem_access_count;
end if;
end if;
end process main_proc;
end process sync_proc;
end architecture behave;

17
src/io_type_pkg.vhd
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@ -16,14 +16,21 @@ package io_types is
end record interface_inst_t;
constant number_of_drivers = 3;
constant address_width = 32;
constant seq_vector_length = 8;
type control_unit_ext_t is record
interface_id_count: in std_logic_vector(number_of_drivers)) downto 0);
address: in std_logic_vector(32 downto 0);
seq_write_count: in std_logic_vector(7 downto 0);
seq_read_count: in std_logic_vector(7 downto 0);
type control_unit_out_t is record
driver_id: std_logic_vector(number_of_drivers - 1 downto 0);
address: std_logic_vector(address_width - 1 downto 0);
seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
ready: std_logic
end record control_unit_format;
type control_unit_in_t is record
driver_id, active_driver: std_logic_vector(number_of_drivers - 1 downto 0);
address: std_logic_vector(address_width - 1 downto 0);
seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0)
end record control_unit_format;
--- PROTOCOL INFORMATION ---
constant interface_inst : interface_inst_t := (
socbridge => ("SoCBridge ", 8, 2, 2)