started working on control unit testbench

src/control_unit.vhd

@@ -19,16 +19,13 @@ architecture behave of control_unit is
     address: std_logic_vector(address_width - 1 downto 0);
     seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
     curr_driver: std_logic_vector(number_of_drivers - 1 downto 0); --one-hot encoded, 0 means disabled
-    ready: std_logic
-  end record type_name;
+    ready: std_logic;
+  end record state_t;
 
-  signal state: state_t := (others => '0', 
-                            others => '0', 
-                            others => '0',
-                            '1');
+  signal state: state_t;
 
 begin
- 
+
   comb_proc: process(control_in, control_out, state)
     variable ored: std_logic := '0';
   begin
@@ -36,6 +33,9 @@ begin
       ored <= ored or control_in.active_driver(i);
     end loop ready_reduction;
     ready <= ored;
+    control_out.driver_id <= state.curr_driver;
+    control_out.address <= state.address;
+    control_out.seq_mem_access_count <= state.seq_mem_access_count;        
   end process comb_proc;
 
   sync_proc: process(clk, state)
@@ -44,16 +44,14 @@ begin
       if rst = '0' then
         state <= (others => '0', 
                   others => '0', 
-                  others => '0');
+                  others => '0',
+                  '1');
       else
         if state.ready = '1' then
           state.address <= control_in.address;
           state.seq_mem_access_count <= control_in.seq_mem_access_count;
           state.curr_driver <= control_in.driver_id;
         end if;
-        control_out.driver_id <= state.curr_driver;
-        control_out.address <= state.address;
-        control_out.seq_mem_access_count <= state.seq_mem_access_count;        
       end if;
     end if;
   end process sync_proc;

src/control_unit_tb.vhd

@@ -0,0 +1,49 @@
+library IEEE;  
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+library work;
+use work.io_types.all;
+
+entity control_unit_tb
+end entity control_unit_tb;
+
+architecture tb of control_unit_tb is
+
+  constant cycle := 10 ns;
+  signal clock := '0';
+  signal finished: std_logic;
+
+
+  component control_unit is
+    port(
+      clk, rst: in std_logic;
+      control_in: in control_unit_in_t;
+      control_out: out control_unit_out_t);
+  end component control_unit;
+
+begin
+ 
+  clock <= not clock after cycle / 2 when finished /= '1';
+
+  control_unit_inst: control_unit
+    port map(
+      clk => clock,
+      rst => reset,
+
+            );
+
+stimulus_proc: process
+begin
+  finished <= '0';
+  
+  finished <= '1';
+end process stimulus_proc; 
+
+monitor_proc: process
+begin
+  finished <= '0';
+
+  finished <= '1';
+end process monitor_proc;
+
+end architecture tb;

src/io_type_pkg.vhd

@@ -15,22 +15,22 @@ package io_types is
     socbridge: ext_protocol_def_t;
   end record interface_inst_t;
 
-  constant number_of_drivers = 3;
-  constant address_width = 32;
-  constant seq_vector_length = 8;
+  constant number_of_drivers: natural := 3;
+  constant address_width: natural := 32;
+  constant seq_vector_length: natural := 8;
 
   type control_unit_out_t is record
     driver_id: std_logic_vector(number_of_drivers - 1 downto 0);
     address: std_logic_vector(address_width - 1 downto 0);
     seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
-    ready: std_logic
-  end record control_unit_format;
+    ready: std_logic;
+  end record control_unit_out_t;
 
   type control_unit_in_t is record
     driver_id, active_driver: std_logic_vector(number_of_drivers - 1 downto 0);
     address: std_logic_vector(address_width - 1 downto 0);
-    seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0)
-  end record control_unit_format;
+    seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
+  end record control_unit_in_t;
   --- PROTOCOL INFORMATION ---
   constant interface_inst : interface_inst_t := (
     socbridge => ("SoCBridge           ", 8, 2, 2)