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testbench debgging

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Adam 2025-03-03 16:46:02 +01:00 committed by Erik Örtenberg
parent e7b4772223
commit 968acd4e3a
2 changed files with 21 additions and 32 deletions
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11
src/control_unit.vhd
View File

@ -23,19 +23,21 @@ architecture behave of control_unit is
end record state_t;
signal state: state_t;
shared variable ored: std_logic;
begin
comb_proc: process(control_in, state)
variable ored: std_logic := '0';
begin
ored := '0';
ready_reduction: for i in 0 to number_of_drivers - 1 loop
ored := ored or control_in.active_driver(i);
end loop ready_reduction;
state.ready <= ored;
control_out.driver_id <= state.curr_driver;
control_out.address <= state.address;
control_out.seq_mem_access_count <= state.seq_mem_access_count;
control_out.ready <= state.ready;
end process comb_proc;
sync_proc: process(clk, state)
@ -45,9 +47,10 @@ begin
state <= ((others => '0'),
(others => '0'),
(others => '0'),
'0');
'1');
else
if state.ready = '1' then
state.ready <= not ored;
if ored = '0' then
state.address <= control_in.address;
state.seq_mem_access_count <= control_in.seq_mem_access_count;
state.curr_driver <= control_in.driver_id;

42
src/control_unit_tb.vhd
View File

@ -1,6 +1,7 @@
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.MATH_REAL.all;
use ieee.numeric_std.all;
library work;
use work.io_types.all;
@ -11,50 +12,41 @@ architecture tb of control_unit_tb is
constant cycle: Time := 10 ns;
signal clock: std_logic := '0';
signal stim_finished, mon_finished: std_logic;
signal reset: std_logic;
signal reset: std_logic := '0';
signal control_input: control_unit_in_t := (
(others => '0'),
(others => '0'),
(others => '0'),
(others => '0'));
"00000011");
signal control_output: control_unit_out_t := (
(others => '0'),
(others => '0'),
(others => '0'),
'0');
(others => '1'),
'1');
signal current_driver : std_logic_vector(2 downto 0) := "000";
shared variable word_counter: natural := 0;
component control_unit is
port(
clk, rst: in std_logic;
control_in: in control_unit_in_t;
control_out: out control_unit_out_t);
end component control_unit;
begin
clock <= not clock after cycle / 2 when (stim_finished and mon_finished) /= '1';
clock <= not clock after cycle / 2;
control_unit_inst: control_unit
control_unit_inst: entity work.control_unit
port map(
clk => clock,
rst => reset,
control_in => control_input,
control_out => control_output
);
);
stimulus_proc: process
begin
stim_finished <= '0';
wait for cycle;
control_input.driver_id <= "010";
control_input.active_driver <= "000";
control_input.address <= x"F0F0F0F0";
control_input.seq_mem_access_count <= "00000111";
word_counter := 3;
report "entering loop with word_counter" & integer'image(word_counter);
for_loop: for i in word_counter - 1 downto 0 loop
@ -63,26 +55,20 @@ begin
end loop for_loop;
control_input.active_driver <= "000";
stim_finished <= '1';
wait until mon_finished = '1';
report "Stim process done";
wait;
end process stimulus_proc;
monitor_proc: process
begin
mon_finished <= '0';
wait for cycle;
wait for cycle;
assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity warning;
assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity warning;
wait until word_counter = 0;
assert control_output.ready = '1' report "control_unit did not signal ready" severity warning;
mon_finished <= '1';
wait until stim_finished = '1';
assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error;
assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
wait for 5 * cycle;
report "Monitor process done";
wait;
end process monitor_proc;