63 lines
1.7 KiB
VHDL
63 lines
1.7 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.MATH_REAL.all;
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library work;
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use work.io_types.all;
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entity control_unit is
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port (
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clk, rst: in std_logic;
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control_in: in control_unit_in_t;
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control_out: out control_unit_out_t
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);
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end entity control_unit;
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architecture behave of control_unit is
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type state_t is record
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address: std_logic_vector(address_width - 1 downto 0);
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seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
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curr_driver: std_logic_vector(number_of_drivers - 1 downto 0); --one-hot encoded, 0 means disabled
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ready: std_logic;
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end record state_t;
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signal state: state_t;
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shared variable ored: std_logic;
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begin
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comb_proc: process(control_in, state)
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begin
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ored := '0';
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ready_reduction: for i in 0 to number_of_drivers - 1 loop
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ored := ored or control_in.active_driver(i);
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end loop ready_reduction;
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control_out.driver_id <= state.curr_driver;
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control_out.address <= state.address;
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control_out.seq_mem_access_count <= state.seq_mem_access_count;
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control_out.ready <= state.ready;
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end process comb_proc;
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sync_proc: process(clk, state)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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state <= ((others => '0'),
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(others => '0'),
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(others => '0'),
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'1');
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else
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state.ready <= not ored;
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if ored = '0' then
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state.address <= control_in.address;
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state.seq_mem_access_count <= control_in.seq_mem_access_count;
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state.curr_driver <= control_in.driver_id;
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end if;
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end if;
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end if;
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end process sync_proc;
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end architecture behave;
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