added most functionality for answering to commands from external socbridge

src/socbridge/socbridge_driver.vhd

@@ -41,6 +41,8 @@ architecture rtl of socbridge_driver is
   signal trans_next_state : translator_state_t;
   --- FSM COMMUNICATION ---
   signal tx_sent_response, rx_received_response    : std_logic;
+  --- MANAGEMENT COMMUNICATION ---
+  signal mgnt_valid_in, mgnt_valid_out, mgnt_ready_out : std_logic;
 begin
   --- DEBUG GLOBAL BINDINGS ---
   -- synthesis translate_off
@@ -203,7 +205,7 @@ begin
         and st.curr_tx_transaction = WRITE_ACK then
           next_rx_state <= IDLE;
         elsif (st.curr_rx_transaction = READ_ADD or st.curr_rx_transaction = READ)
-        and st.curr_tx_transaction = READ_RESPONSE then
+        and st.curr_tx_transaction = READ_RESPONSE and st.tx_stage = 0 then
           next_rx_state <= IDLE;
         else 
           next_rx_state <= RX_AWAIT;
@@ -233,15 +235,18 @@ begin
         end if;
       when TX_AWAIT =>
       when ADDR1 =>
-        socbridge_driver_to_ext_data_cmd := st.curr_addr(31 downto 24);
+        socbridge_driver_to_ext_data_cmd := st.curr_tx_addr(31 downto 24);
       when ADDR2 =>
-        socbridge_driver_to_ext_data_cmd := st.curr_addr(23 downto 16);
+        socbridge_driver_to_ext_data_cmd := st.curr_tx_addr(23 downto 16);
       when ADDR3 =>
-        socbridge_driver_to_ext_data_cmd := st.curr_addr(15 downto 8);
+        socbridge_driver_to_ext_data_cmd := st.curr_tx_addr(15 downto 8);
       when ADDR4 =>
-        socbridge_driver_to_ext_data_cmd := st.curr_addr(7 downto 0);
+        socbridge_driver_to_ext_data_cmd := st.curr_tx_addr(7 downto 0);
     end case;
     --- ### RX_STATE BASED OUTPUT ### ---
+    mgnt_valid_in <= '0';
+    mgnt_valid_out <= '0';
+    mgnt_ready_out <= '0';
     case st.curr_rx_state is
       when IDLE => 
       when RX_HEADER =>
@@ -254,6 +259,9 @@ begin
         socbridge_driver_to_ip.payload <= st.ext_to_socbridge_driver_reg.data;
         socbridge_driver_to_ip.write_enable_in <= '1';
       when RX_AWAIT =>
+        if st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
+          mgnt_valid_in <= '1';
+        end if;
       when ADDR1 =>
       when ADDR2 =>
       when ADDR3 =>
@@ -290,9 +298,16 @@ begin
         end if;
     end case;
 
-      --- Combinatorial output based on state
+    --- NEXT TX TRANSACTION ---
     next_tx_transaction := NO_OP;
     next_tx_data_size <= 0;
+    if trans_st.curr_state = IDLE and st.curr_rx_state = RX_AWAIT then
+      if st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
+        next_tx_transaction := WRITE_ACK;
+      elsif st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD then
+        next_tx_transaction := READ_RESPONSE;
+      end if;
+    end if;
     case trans_st.curr_state is
       when IDLE =>
       when SEND =>
@@ -336,7 +351,10 @@ begin
       st.curr_tx_transaction <= NO_OP;
       st.curr_rx_transaction <= NO_OP;
       st.tx_data_size <= 0;
-      st.curr_addr <= (others => '0');
+      st.curr_tx_addr <= (others => '0');
+      st.curr_rx_addr <= (others => '0');
+      st.curr_write_data <= (others => '0');
+      st.curr_read_data <= (others => '0');
 
     elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then
       st.ext_to_socbridge_driver_reg.data <= ext_to_socbridge_driver_rec.data;
@@ -351,7 +369,7 @@ begin
         when IDLE =>
           st.curr_tx_transaction <= next_tx_transaction;   
           st.tx_data_size <= next_tx_data_size;
-          st.curr_addr <= trans_st.curr_inst.address;
+          st.curr_tx_addr <= trans_st.curr_inst.address;
           if next_tx_transaction = WRITE_ADD or next_tx_transaction = WRITE
           or next_tx_transaction = READ_RESPONSE then
             st.tx_stage <= next_tx_data_size;
@@ -377,6 +395,10 @@ begin
           else
             st.rx_stage <= 0;
           end if;
+        when RX_HEADER => 
+          if st.curr_rx_transaction = READ then
+            st.curr_rx_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_addr) + 4), 32));
+          end if;
         when RX_R_BODY =>
           if st.rx_stage > 0 then
             st.rx_stage <= st.rx_stage - 1;
@@ -384,7 +406,16 @@ begin
         when RX_W_BODY =>
           if st.rx_stage > 0 then
             st.rx_stage <= st.rx_stage - 1;
+            st.curr_write_data((st.rx_stage) * 8 - 1 downto (st.rx_stage - 1) * 8) <= st.ext_to_socbridge_driver_reg.data;
           end if;
+        when ADDR1 =>
+          st.curr_rx_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
+        when ADDR2 =>
+          st.curr_rx_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
+        when ADDR3 =>
+          st.curr_rx_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
+        when ADDR4 =>
+          st.curr_rx_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
         when others => 
       end case;
     end if;

src/socbridge/socbridge_driver_tb_pkg.vhd

@@ -42,7 +42,10 @@ package socbridge_driver_tb_pkg is
     ext_to_socbridge_driver_reg, socbridge_driver_to_ext_reg : ext_protocol_t; 
     tx_stage, rx_stage : NATURAL;
     tx_data_size, rx_data_size : integer;
-    curr_addr : std_logic_vector(31 downto 0);
+    curr_write_data : std_logic_vector(31 downto 0);
+    curr_read_data : std_logic_vector(31 downto 0);
+    curr_tx_addr : std_logic_vector(31 downto 0);
+    curr_rx_addr : std_logic_vector(31 downto 0);
   end record state_rec_t;
   impure function calc_parity(
     d : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0)