Refactoring done

src/control_socbridge_merge/control_socbridge_tb.vhd

@@ -7,24 +7,24 @@ library socbridge;
 use socbridge.socbridge_driver_tb_pkg.all;
 library controller;
 
-entity controller_socbridge_tb is
+entity control_socbridge_tb is
-end entity controller_socbridge_tb;
+end entity control_socbridge_tb;
 
-architecture tb of controller_socbridge_tb is
+architecture tb of control_socbridge_tb is
 
-  constant CLK_PERIOD : Time := 10 ns;
+  constant CLK_PERIOD                           : Time := 10 ns;
-  constant SIMULATION_CYCLE_COUNT : integer := 2000;
+  constant SIMULATION_CYCLE_COUNT               : integer := 2000;
-  signal clk, rst : std_logic := '0';
+  signal clk, rst                               : std_logic := '0';
-  signal cu_to_sb_cmd: command_t;
+  signal controller_to_socbridge_driver_cmd     : command_t;
-  signal cu_to_sb_address: std_logic_vector(31 downto 0);
+  signal controller_to_socbridge_driver_address : std_logic_vector(31 downto 0);
-  signal cmd_size : positive;
+  signal cmd_size                               : positive;
-  signal ext_socbridge_in  :  ext_socbridge_in_t := (
+  signal ext_to_socbridge_driver                : ext_to_socbridge_driver_t := (
     payload => (others => '0'),
     control => (others => '0')
   );
-  signal ext_socbridge_out :  ext_socbridge_out_t;
+  signal socbridge_driver_to_ext    :  socbridge_driver_to_ext_t;
-  signal int_socbridge_out  :  int_socbridge_out_t;
+  signal socbridge_driver_to_buffer :  socbridge_driver_to_buffer_t;
-  signal int_socbridge_in :  int_socbridge_in_t := (
+  signal buffer_to_socbridge_driver :  buffer_to_socbridge_driver_t := (
     payload => (others => '0'),
     write_enable_out => '0',
     is_full_in => '0'
@@ -35,12 +35,12 @@ architecture tb of controller_socbridge_tb is
     seq_mem_access_count => 0,
     cmd => "00"
   );
-  signal driver_to_controller: driver_to_controller_t := (is_active => '0');
+  signal socbridge_driver_to_controller: socbridge_driver_to_controller_t := (is_active => '0');
   signal controller_to_cpu: controller_to_cpu_t;
-  signal controller_to_driver: controller_to_driver_t;
+  signal controller_to_socbridge_driver: controller_to_socbridge_driver_t;
 
-  signal curr_word : std_logic_vector(ext_socbridge_in.payload'length - 1 downto 0);
+  signal curr_word : std_logic_vector(ext_to_socbridge_driver.payload'length - 1 downto 0);
-  signal expected_out : std_logic_vector(ext_socbridge_out.payload'length - 1 downto 0);
+  signal expected_out : std_logic_vector(socbridge_driver_to_ext.payload'length - 1 downto 0);
 
   procedure fail(error_msg : string) is 
   begin
@@ -57,19 +57,19 @@ architecture tb of controller_socbridge_tb is
     end if;
   end procedure;
   
-  procedure check_data_out(correct_data: std_logic_vector(ext_socbridge_out.payload'length - 1 downto 0)) is
+  procedure check_data_out(correct_data: std_logic_vector(socbridge_driver_to_ext.payload'length - 1 downto 0)) is
   begin
-    if(not (correct_data = ext_socbridge_out.payload)) then
+    if(not (correct_data = socbridge_driver_to_ext.payload)) then
-      report "Data out is not what was expected, found " & to_string(ext_socbridge_out.payload)
+      report "Data out is not what was expected, found " & to_string(socbridge_driver_to_ext.payload)
             & " but expected " & to_string(correct_data) severity error;
       fail("Data out");
     end if;
   end procedure;
 
-  procedure check_parity(correct_data: std_logic_vector(ext_socbridge_out.payload'length - 1 downto 0)) is
+  procedure check_parity(correct_data: std_logic_vector(socbridge_driver_to_ext.payload'length - 1 downto 0)) is
   begin
-    if(not (calc_parity(correct_data) = calc_parity(ext_socbridge_out.payload))) then
+    if(not (calc_parity(correct_data) = calc_parity(socbridge_driver_to_ext.payload))) then
-      report "Parity out is not what was expected, found " & std_logic'image(calc_parity(ext_socbridge_out.payload))
+      report "Parity out is not what was expected, found " & std_logic'image(calc_parity(socbridge_driver_to_ext.payload))
             & " but expected " & std_logic'image(calc_parity(correct_data))  severity error;
       fail("Parity out");
     end if;
@@ -78,27 +78,27 @@ architecture tb of controller_socbridge_tb is
 begin
   socbridge_inst: entity socbridge.socbridge_driver
     port map(
-      clk      => clk,
+      clk                            => clk,
-      rst      => rst,
+      rst                            => rst,
-      ctrl_in  => controller_to_driver,
+      controller_to_socbridge_driver => controller_to_socbridge_driver,
-      ctrl_out => driver_to_controller, 
+      socbridge_driver_to_controller => socbridge_driver_to_controller, 
-      ext_in   => ext_socbridge_in,
+      ext_to_socbridge_driver        => ext_to_socbridge_driver,
-      ext_out  => ext_socbridge_out,
+      socbridge_driver_to_ext        => socbridge_driver_to_ext,
-      int_in   => int_socbridge_in,
+      buffer_to_socbridge_driver     => buffer_to_socbridge_driver,
-      int_out  => int_socbridge_out
+      socbridge_driver_to_buffer     => socbridge_driver_to_buffer
     );
 
   controller_unit_inst: entity controller.control_unit
     port map(
-      clk             => clk,
+      clk                            => clk,
-      rst             => rst,
+      rst                            => rst,
-      cpu_to_controller  => cpu_to_controller,
+      cpu_to_controller              => cpu_to_controller,
-      controller_to_cpu => controller_to_cpu,
+      controller_to_cpu              => controller_to_cpu,
-      driver_to_controller  => driver_to_controller,
+      socbridge_driver_to_controller => socbridge_driver_to_controller,
-      controller_to_driver => controller_to_driver
+      controller_to_socbridge_driver => controller_to_socbridge_driver
   );
   
-  ext_socbridge_in.control(1) <= clk;
+  ext_to_socbridge_driver.control(1) <= clk;
   controller_clock_proc: process
   begin
   for i in 0 to SIMULATION_CYCLE_COUNT - 1 loop
@@ -121,21 +121,21 @@ begin
     rst <= '0';
     cpu_to_controller.address <= x"FA0FA0FA";
     cpu_to_controller.cmd <= "01";
-    wait until driver_to_controller.is_active = '1';
+    wait until socbridge_driver_to_controller.is_active = '1';
     report "Task received in driver, awaiting completion...";
     cpu_to_controller.address <= (others => '0');
     cpu_to_controller.cmd <= "00";
-    wait until driver_to_controller.is_active = '0';
+    wait until socbridge_driver_to_controller.is_active = '0';
     wait for CLK_PERIOD;
     report "Task completed in driver, sending next task...";
     cpu_to_controller.address <= x"FA0FA0FA";
     cpu_to_controller.cmd <= "10";
     wait for CLK_PERIOD;
-    wait until driver_to_controller.is_active = '1';
+    wait until socbridge_driver_to_controller.is_active = '1';
     report "Task received in driver, awaiting completion...";
     cpu_to_controller.address <= (others => '0');
     cpu_to_controller.cmd <= "00";
-    wait until driver_to_controller.is_active = '0';
+    wait until socbridge_driver_to_controller.is_active = '0';
     wait for CLK_PERIOD;
     report "Task completed in driver, ending simulation stimulus";
     cpu_to_controller.address <= (others => '0');
@@ -148,8 +148,8 @@ begin
 
   external_stimulus_signal: process(curr_word)
   begin
-    ext_socbridge_in.payload <= curr_word;
+    ext_to_socbridge_driver.payload <= curr_word;
-    ext_socbridge_in.control(0) <= calc_parity(curr_word);
+    ext_to_socbridge_driver.control(0) <= calc_parity(curr_word);
   end process external_stimulus_signal;
 
   external_stimulus: process
@@ -197,19 +197,19 @@ begin
   internal_stimulus: process
     variable input : positive := 1;
   begin
-    int_socbridge_in.is_full_in <= '0';
+    buffer_to_socbridge_driver.is_full_in <= '0';
-    int_socbridge_in.write_enable_out <= '0';
+    buffer_to_socbridge_driver.write_enable_out <= '0';
     wait for 3 * CLK_PERIOD;
     -- stimulus goes here
-    int_socbridge_in.write_enable_out <= '1';
+    buffer_to_socbridge_driver.write_enable_out <= '1';
-    int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
+    buffer_to_socbridge_driver.payload <= std_logic_vector(to_unsigned(input, buffer_to_socbridge_driver.payload'length));
     input := input + 1 mod 256;
-    wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
+    wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0';
     wait until falling_edge(clk);
     for x in 0 to 1000 loop
-      int_socbridge_in.payload <= std_logic_vector(to_unsigned(input, int_socbridge_in.payload'length));
+      buffer_to_socbridge_driver.payload <= std_logic_vector(to_unsigned(input, buffer_to_socbridge_driver.payload'length));
       input := input + 1 mod 256;
-      wait until rising_edge(clk) and int_socbridge_out.is_full_out = '0';
+      wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0';
       wait until falling_edge(clk);
     end loop;
     wait;

src/controller/control_unit.vhd

@@ -10,8 +10,8 @@ entity control_unit is
     clk, rst        : in  std_logic;
     cpu_to_controller  : in  cpu_to_controller_t;
     controller_to_cpu : out controller_to_cpu_t;
-    driver_to_controller  : in  driver_to_controller_t;
+    socbridge_driver_to_controller  : in  socbridge_driver_to_controller_t;
-    controller_to_driver : out controller_to_driver_t
+    controller_to_socbridge_driver : out controller_to_socbridge_driver_t
   );
 
 end entity control_unit;
@@ -20,7 +20,7 @@ architecture behave of control_unit is
   type state_t is record
     address: std_logic_vector(address_width - 1 downto 0);
     seq_mem_access_count: integer;
-    curr_driver: std_logic_vector(number_of_drivers - 1 downto 0); --one-hot encoded, 0 means disabled
+    curr_driver: std_logic; 
     ready: std_logic;
     instruction: instruction_command_t;
   end record state_t;
@@ -31,17 +31,17 @@ architecture behave of control_unit is
 
 begin
 
-  comb_proc: process(cpu_to_controller, driver_to_controller, state)
+  comb_proc: process(cpu_to_controller, socbridge_driver_to_controller, state)
   begin
     ored := '0';
     ready_reduction: for i in 0 to number_of_drivers - 1 loop
-      ored := ored or driver_to_controller.active_driver(i);
+      ored := ored or socbridge_driver_to_controller.is_active;
     end loop ready_reduction;
-    controller_to_driver.driver_id <= state.curr_driver;
+    controller_to_socbridge_driver.request <= state.curr_driver;
-    controller_to_driver.address <= state.address;
+    controller_to_socbridge_driver.address <= state.address;
-    controller_to_driver.seq_mem_access_count <= state.seq_mem_access_count;        
+    controller_to_socbridge_driver.seq_mem_access_count <= state.seq_mem_access_count;        
     controller_to_cpu.ready <= state.ready;
-    controller_to_driver.instruction <= state.instruction;
+    controller_to_socbridge_driver.instruction <= state.instruction;
   end process comb_proc;
 
   sync_proc: process(clk, state)
@@ -50,7 +50,7 @@ begin
       if rst = '1' then
         state <= ((others => '0'), 
                   0, 
-                  (others => '0'),
+                  '0',
                   '1',
                   NO_OP);
       else
@@ -58,7 +58,7 @@ begin
         if ored = '0' then
           state.address <= cpu_to_controller.address;
           state.seq_mem_access_count <= cpu_to_controller.seq_mem_access_count;
-          state.curr_driver <= cpu_to_controller.driver_id;
+          state.curr_driver <= cpu_to_controller.driver_id(0);
           with cpu_to_controller.cmd select
             state.instruction <= WRITE when "01",
                                  READ  when "10",
@@ -66,7 +66,7 @@ begin
         else
           state <= ((others => '0'), 
                     0, 
-                    (others => '0'),
+                    '0',
                     '1',
                     NO_OP);
         end if;

src/controller/control_unit_tb.vhd

@@ -14,14 +14,14 @@ architecture tb of control_unit_tb is
   constant cycle: Time := 10 ns;
   signal clock: std_logic := '0';
   signal reset: std_logic := '0';
-  signal ext_control_input: ext_control_unit_in_t := (
+  signal cpu_to_controller: cpu_to_controller_t := (
                                               (others => '0'),
                                               (others => '0'),
                                               0,
                                               "00");
-  signal int_control_input: int_control_unit_in_t := (active_driver => (others => '0'));
+  signal socbridge_driver_to_controller: socbridge_driver_to_controller_t := (is_active => '0');
-  signal ext_control_output: ext_control_unit_out_t;
+  signal controller_to_cpu: controller_to_cpu_t;
-  signal int_control_output: int_control_unit_out_t;
+  signal controller_to_socbridge_driver: controller_to_socbridge_driver_t;
   signal current_driver : std_logic_vector(0 downto 0) := "0";
   shared variable word_counter: natural := 0;
 
@@ -40,21 +40,21 @@ begin
     port map(
     clk             => clock,
     rst             => reset,
-    ext_control_in  => ext_control_input,
+    cpu_to_controller  => cpu_to_controller,
-    ext_control_out => ext_control_output,
+    controller_to_cpu => controller_to_cpu,
-    int_control_in  => int_control_input,
+    socbridge_driver_to_controller  => socbridge_driver_to_controller,
-    int_control_out => int_control_output
+    controller_to_socbridge_driver => controller_to_socbridge_driver
     );
 
 stimulus_proc: process
 begin
   wait for cycle;
 
-  ext_control_input.driver_id <= "1";
+  cpu_to_controller.driver_id <= "1";
-  int_control_input.active_driver <= "0";
+  socbridge_driver_to_controller.is_active <= '0';
-  ext_control_input.address <= x"F0F0F0F0";
+  cpu_to_controller.address <= x"F0F0F0F0";
-  ext_control_input.seq_mem_access_count <= 3;
+  cpu_to_controller.seq_mem_access_count <= 3;
-  ext_control_input.cmd <= "01";
+  cpu_to_controller.cmd <= "01";
   word_counter := 3;
   wait for cycle;
   current_driver <= "1";
@@ -65,7 +65,7 @@ begin
     report "words remaining are " & integer'image(i);
   end loop for_loop;
   
-  int_control_input.active_driver <= "0";
+  socbridge_driver_to_controller.is_active <= '0';
   report "Stim process done";
   wait;
 end process stimulus_proc; 
@@ -76,9 +76,9 @@ begin
   wait for cycle;
 
   wait for cycle;
-  assert int_control_output.driver_id = "1" report "Incorrect driver_id from control_unit" severity error;
+  assert controller_to_socbridge_driver.request = '1' report "Incorrect driver_id from control_unit" severity error;
-  assert int_control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
+  assert controller_to_socbridge_driver.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
-  assert int_control_output.instruction = WRITE report "Incorrect memory op from control_unit" severity error;
+  assert controller_to_socbridge_driver.instruction = WRITE report "Incorrect memory op from control_unit" severity error;
 
   wait for 5 * cycle;
   reset <= '1';

src/ganimede/ganimede.vhd

@@ -43,10 +43,10 @@ architecture rtl of ganimede is
     port(
       clk     : in std_logic;
       reset   : in std_logic;
-      ext_in  : in ext_socbridge_in_t;
+      ext_in  : in ext_to_socbridge_driver_t;
-      ext_out : out ext_socbridge_out_t;
+      ext_out : out socbridge_driver_to_ext_t;
-      int_in  : out int_socbridge_in_t;
+      int_in  : out buffer_to_socbridge_driver_t;
-      int_out : in int_socbridge_out_t
+      int_out : in socbridge_driver_to_buffer_t
     );
   end component;
 

src/ganimede/io_type_pkg.vhd

@@ -35,27 +35,27 @@ package io_types is
     ready: std_logic;
   end record controller_to_cpu_t;
 
-  --type controller_to_driver_t is record
+  --type controller_to_socbridge_driver_t is record
   --  driver_id: std_logic_vector(number_of_drivers - 1 downto 0);
   --  address: std_logic_vector(address_width - 1 downto 0);
   --  seq_mem_access_count: integer;
   --  instruction: instruction_command_t;
-  --end record controller_to_driver_t;
+  --end record controller_to_socbridge_driver_t;
 
-  --type driver_to_controller_t is record
+  --type socbridge_driver_to_controller_t is record
   --  active_driver: std_logic_vector(number_of_drivers - 1 downto 0);
-  --end record driver_to_controller_t;
+  --end record socbridge_driver_to_controller_t;
 
-  type driver_to_controller_t is record
+  type socbridge_driver_to_controller_t is record
     is_active : std_logic;    
-  end record driver_to_controller_t;
+  end record socbridge_driver_to_controller_t;
 
-  type controller_to_driver_t is record
+  type controller_to_socbridge_driver_t is record
     request: std_logic;
     address: std_logic_vector(address_width - 1 downto 0);
     seq_mem_access_count: integer;
     instruction: instruction_command_t;
-  end record controller_to_driver_t;
+  end record controller_to_socbridge_driver_t;
 
   --- PROTOCOL INFORMATION ---
   constant interface_inst : interface_inst_t := (
@@ -63,40 +63,40 @@ package io_types is
   ); 
 
   --- AUTOGENERATED TYPES ---
-  type ext_socbridge_in_t is record 
+  type ext_to_socbridge_driver_t is record 
     payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
     control : STD_LOGIC_VECTOR(interface_inst.socbridge.control_width_in - 1 downto 0);
-  end record ext_socbridge_in_t;
+  end record ext_to_socbridge_driver_t;
 
-  type ext_socbridge_out_t is record 
+  type socbridge_driver_to_ext_t is record 
     payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
     control : STD_LOGIC_VECTOR(interface_inst.socbridge.control_width_in - 1 downto 0);
-  end record ext_socbridge_out_t;
+  end record socbridge_driver_to_ext_t;
 
-  type int_socbridge_out_t is record 
+  type socbridge_driver_to_buffer_t is record 
     payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
     write_enable_in, is_full_out : std_logic;
-  end record int_socbridge_out_t;
+  end record socbridge_driver_to_buffer_t;
 
-  type int_socbridge_in_t is record 
+  type buffer_to_socbridge_driver_t is record 
     payload : STD_LOGIC_VECTOR(interface_inst.socbridge.payload_width - 1 downto 0);
     write_enable_out, is_full_in : std_logic;
-  end record int_socbridge_in_t;
+  end record buffer_to_socbridge_driver_t;
 
   type ext_interface_in_t is record
-    socbridge : ext_socbridge_in_t;     
+    socbridge : ext_to_socbridge_driver_t;     
   end record ext_interface_in_t;
 
   type ext_interface_out_t is record
-    socbridge : ext_socbridge_out_t;
+    socbridge : socbridge_driver_to_ext_t;
   end record ext_interface_out_t;
 
   type int_interface_out_t is record
-    socbridge : int_socbridge_out_t;
+    socbridge : socbridge_driver_to_buffer_t;
   end record int_interface_out_t;
 
   type int_interface_in_t is record
-    socbridge : int_socbridge_in_t;
+    socbridge : buffer_to_socbridge_driver_t;
   end record int_interface_in_t;
 
 end package io_types;

src/socbridge/socbridge_driver.vhd

@@ -9,30 +9,30 @@ use socbridge.socbridge_driver_tb_pkg.all;
 
 entity socbridge_driver is
   port(
-    clk     : in std_logic;
+    clk                            : in std_logic;
-    rst     : in std_logic;
+    rst                            : in std_logic;
-    ctrl_in : in controller_to_driver_t;
+    controller_to_socbridge_driver : in controller_to_socbridge_driver_t;
-    ctrl_out: out driver_to_controller_t;
+    socbridge_driver_to_controller : out socbridge_driver_to_controller_t;
-    ext_in  : in ext_to_socbridge_driver_t;
+    ext_to_socbridge_driver        : in ext_to_socbridge_driver_t;
-    ext_out : out socbridge_driver_to_ext_t;
+    socbridge_driver_to_ext        : out socbridge_driver_to_ext_t;
-    int_out : out int_socbridge_out_t;
+    socbridge_driver_to_buffer     : out socbridge_driver_to_buffer_t;
-    int_in  : in int_socbridge_in_t
+    buffer_to_socbridge_driver     : in buffer_to_socbridge_driver_t
   );
 end entity socbridge_driver;
 
 architecture rtl of socbridge_driver is
   
-  signal next_parity_out : std_logic;
+  signal next_parity_out                           : std_logic;
-  signal ext_in_rec : ext_protocol_t;
+  signal ext_to_socbridge_driver_rec               : ext_protocol_t;
-  shared variable ext_out_data_cmd : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
+  shared variable socbridge_driver_to_ext_data_cmd : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
-  signal test : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
+  signal test                                      : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
-  signal next_cmd : command_t;
+  signal next_cmd                                  : command_t;
-  signal next_cmd_size : integer;
+  signal next_cmd_size                             : integer;
-  signal next_state : state_t;
+  signal next_state                                : state_t;
-  signal curr_cmd_bits : std_logic_vector(4 downto 0);
+  signal curr_cmd_bits                             : std_logic_vector(4 downto 0);
-  signal curr_response : response_t;
+  signal curr_response                             : response_t;
-  signal curr_response_bits : std_logic_vector(4 downto 0);
+  signal curr_response_bits                        : std_logic_vector(4 downto 0);
-  signal st : state_rec_t;
+  signal st                                        : state_rec_t;
   --- TRANSLATOR ---
   signal trans_st : translator_state_rec_t;
   signal trans_next_state : translator_state_t;
@@ -40,32 +40,32 @@ begin
   --- DEBUG GLOBAL BINDINGS ---
   -- synthesis translate_off
   G_next_parity_out <= next_parity_out;
-  G_ext_in_rec <= ext_in_rec;
+  G_ext_to_socbridge_driver_rec <= ext_to_socbridge_driver_rec;
   G_next_state <= next_state;
-  G_ext_out_data_cmd <=test;
+  G_socbridge_driver_to_ext_data_cmd <=test;
   G_curr_command_bits <= curr_cmd_bits;
   G_curr_response <= curr_response;
   G_curr_response_bits <= curr_response_bits;
   G_st <= st;
   G_trans_st <= trans_st;
   -- synthesis translate_on
-  ext_in_rec.data <= ext_in.payload;
+  ext_to_socbridge_driver_rec.data <= ext_to_socbridge_driver.payload;
-  ext_in_rec.clk <= ext_in.control(1);
+  ext_to_socbridge_driver_rec.clk <= ext_to_socbridge_driver.control(1);
-  ext_in_rec.parity <= ext_in.control(0);
+  ext_to_socbridge_driver_rec.parity <= ext_to_socbridge_driver.control(0);
 
   -- Helpful Bindings --
-  curr_response_bits <= ext_in.payload(7 downto 3); -- CANT USE EXT_IN_REC here for some reason, the assignment becomes stasteful
+  curr_response_bits <= ext_to_socbridge_driver.payload(7 downto 3); -- CANT USE ext_to_socbridge_driver_REC here for some reason, the assignment becomes stasteful
                                                     -- Not sure that the two process method is helping here: if this was a normal
                                                     -- signal assignment there would be no confusion.
-                                                    -- in the case ... <= ext_in_rec we get
+                                                    -- in the case ... <= ext_to_socbridge_driver_rec we get
-                                                    -- curr_resp | ext_in_rec | ext_in
+                                                    -- curr_resp | ext_to_socbridge_driver_rec | ext_to_socbridge_driver
                                                     -- 00000     | 00000000   | 00001001 
                                                     -- 00000     | 00001001   | 00001001 
                                                     -- 00001     | 00001001   | 00001001 
                                                     -- 00001     | 00001001   | 00001001 
                                                     -- 
-                                                    -- but in the case ... <= ext_in we get
+                                                    -- but in the case ... <= ext_to_socbridge_driver we get
-                                                    -- curr_resp | ext_in_rec | ext_in
+                                                    -- curr_resp | ext_to_socbridge_driver_rec | ext_to_socbridge_driver
                                                     -- 00000     | 00000000   | 00001001 
                                                     -- 00001     | 00001001   | 00001001 
                                                     -- 00001     | 00001001   | 00001001 
@@ -77,12 +77,12 @@ begin
                       READ_RESPONSE when "01000",
                       READ_RESPONSE when "01100",
                       NO_OP when others;
-  comb_proc: process(ext_in, int_in, curr_response, st, ctrl_in, trans_st)
+  comb_proc: process(ext_to_socbridge_driver, buffer_to_socbridge_driver, curr_response, st, controller_to_socbridge_driver, trans_st)
   begin
     -- Outputs 
-    ext_out <= create_io_type_out_from_ext_protocol(st.ext_out_reg);
+    socbridge_driver_to_ext <= create_io_type_out_from_ext_protocol(st.socbridge_driver_to_ext_reg);
     with trans_st.curr_state select
-    ctrl_out.is_active <= '0' when IDLE,
+    socbridge_driver_to_controller.is_active <= '0' when IDLE,
                           '1' when others;
 
     --- State Transition Diagram ---
@@ -193,58 +193,58 @@ begin
     end case;
     
   --- Combinatorial output based on current state ---
-    ext_out_data_cmd := (others => '0');
+    socbridge_driver_to_ext_data_cmd := (others => '0');
-    int_out.is_full_out <= '1';
+    socbridge_driver_to_buffer.is_full_out <= '1';
-    int_out.write_enable_in <= '0';
+    socbridge_driver_to_buffer.write_enable_in <= '0';
-    int_out.payload <= (others => '0');
+    socbridge_driver_to_buffer.payload <= (others => '0');
     case st.curr_state is
       when IDLE => 
         if st.curr_cmd = WRITE or st.curr_cmd = WRITE_ADD then
-          ext_out_data_cmd := get_cmd_bits(st.curr_cmd) & get_size_bits(st.curr_cmd_size);
+          socbridge_driver_to_ext_data_cmd := get_cmd_bits(st.curr_cmd) & get_size_bits(st.curr_cmd_size);
         elsif st.curr_cmd = READ or st.curr_cmd = READ_ADD then
-          ext_out_data_cmd := get_cmd_bits(st.curr_cmd) & get_size_bits(st.curr_cmd_size);
+          socbridge_driver_to_ext_data_cmd := get_cmd_bits(st.curr_cmd) & get_size_bits(st.curr_cmd_size);
         else
         end if;       
       when TX_HEADER =>
         if st.curr_cmd = WRITE_ADD then
-          ext_out_data_cmd := st.curr_addr(7 downto 0);
+          socbridge_driver_to_ext_data_cmd := st.curr_addr(7 downto 0);
         else 
-          ext_out_data_cmd := int_in.payload;
+          socbridge_driver_to_ext_data_cmd := buffer_to_socbridge_driver.payload;
-          int_out.is_full_out <= '0';
+          socbridge_driver_to_buffer.is_full_out <= '0';
         end if;
       when TX_BODY =>
         if st.write_stage > 0 then
-          int_out.is_full_out <= '0';
+          socbridge_driver_to_buffer.is_full_out <= '0';
-          ext_out_data_cmd := int_in.payload;
+          socbridge_driver_to_ext_data_cmd := buffer_to_socbridge_driver.payload;
         else 
-          ext_out_data_cmd := (others => '0');
+          socbridge_driver_to_ext_data_cmd := (others => '0');
         end if;
       when TX_ACK =>
       when RX_HEADER =>
         if st.curr_cmd = READ_ADD then
-          ext_out_data_cmd := st.curr_addr(7 downto 0);
+          socbridge_driver_to_ext_data_cmd := st.curr_addr(7 downto 0);
         end if; 
       when RX_RESPONSE =>
       when RX_BODY =>
-        int_out.payload <= st.ext_in_reg.data;
+        socbridge_driver_to_buffer.payload <= st.ext_to_socbridge_driver_reg.data;
-        int_out.write_enable_in <= '1';
+        socbridge_driver_to_buffer.write_enable_in <= '1';
       when ADDR1 =>
-        ext_out_data_cmd := st.curr_addr(15 downto 8);
+        socbridge_driver_to_ext_data_cmd := st.curr_addr(15 downto 8);
       when ADDR2 =>
-        ext_out_data_cmd := st.curr_addr(23 downto 16);
+        socbridge_driver_to_ext_data_cmd := st.curr_addr(23 downto 16);
       when ADDR3 =>
-        ext_out_data_cmd := st.curr_addr(31 downto 24);
+        socbridge_driver_to_ext_data_cmd := st.curr_addr(31 downto 24);
       when ADDR4 =>
         if st.curr_cmd = WRITE_ADD then
-          int_out.is_full_out <= '0';
+          socbridge_driver_to_buffer.is_full_out <= '0';
-          ext_out_data_cmd := int_in.payload;
+          socbridge_driver_to_ext_data_cmd := buffer_to_socbridge_driver.payload;
-          report integer'image(to_integer(signed(ext_out_data_cmd))) & " "&  integer'image(to_integer(signed(int_in.payload)));
+          report integer'image(to_integer(signed(socbridge_driver_to_ext_data_cmd))) & " "&  integer'image(to_integer(signed(buffer_to_socbridge_driver.payload)));
         end if;
     end case;
-    next_parity_out <= calc_parity(ext_out_data_cmd);
+    next_parity_out <= calc_parity(socbridge_driver_to_ext_data_cmd);
     --- DEBUG GLOBAL BINDINGS ---
     -- synthesis translate_off
-    test <= ext_out_data_cmd;
+    test <= socbridge_driver_to_ext_data_cmd;
     -- synthesis translate_on
     --- TRANSLATOR ---
 
@@ -309,13 +309,13 @@ begin
 
   end process comb_proc;
   -- Process updating internal registers based on primary clock
-  seq_proc: process(ext_in_rec.clk, rst, clk)
+  seq_proc: process(ext_to_socbridge_driver_rec.clk, rst, clk)
   begin
     if(rst = '1') then
-      st.ext_in_reg.data <= (others => '0');
+      st.ext_to_socbridge_driver_reg.data <= (others => '0');
-      st.ext_out_reg.data <= (others => '0');
+      st.socbridge_driver_to_ext_reg.data <= (others => '0');
-      st.ext_out_reg.clk <= '0';
+      st.socbridge_driver_to_ext_reg.clk <= '0';
-      st.ext_out_reg.parity <= '1';
+      st.socbridge_driver_to_ext_reg.parity <= '1';
       st.curr_state <= IDLE;
       st.write_stage <= 0;
       st.read_stage <= 0;
@@ -323,13 +323,13 @@ begin
       st.curr_cmd_size <= 0;
       st.curr_addr <= (others => '0');
 
-    elsif(rising_edge(ext_in_rec.clk)) then
+    elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then
-      st.ext_in_reg.data <= ext_in_rec.data;
+      st.ext_to_socbridge_driver_reg.data <= ext_to_socbridge_driver_rec.data;
-      st.ext_in_reg.clk <= ext_in_rec.clk;
+      st.ext_to_socbridge_driver_reg.clk <= ext_to_socbridge_driver_rec.clk;
-      st.ext_in_reg.parity <= ext_in_rec.parity;
+      st.ext_to_socbridge_driver_reg.parity <= ext_to_socbridge_driver_rec.parity;
-      st.ext_out_reg.data <= ext_out_data_cmd;
+      st.socbridge_driver_to_ext_reg.data <= socbridge_driver_to_ext_data_cmd;
-      st.ext_out_reg.clk <= not st.ext_out_reg.clk;
+      st.socbridge_driver_to_ext_reg.clk <= not st.socbridge_driver_to_ext_reg.clk;
-      st.ext_out_reg.parity <= next_parity_out; 
+      st.socbridge_driver_to_ext_reg.parity <= next_parity_out; 
       st.curr_state <= next_state;
       case st.curr_state is
         when IDLE =>
@@ -374,8 +374,8 @@ begin
       trans_st.curr_state <= trans_next_state;
       case trans_st.curr_state is
         when IDLE =>
-          if ctrl_in.request = '1' then
+          if controller_to_socbridge_driver.request = '1' then
-            trans_st.curr_inst <= ctrl_in;
+            trans_st.curr_inst <= controller_to_socbridge_driver;
           else 
           end if;
           trans_st.is_first_word <= '1';
@@ -395,6 +395,4 @@ begin
     end if;
   end process seq_proc;
 
-
-
 end architecture rtl;

src/socbridge/socbridge_driver_tb.vhd

@@ -17,14 +17,14 @@ architecture tb of socbridge_driver_tb is
   signal cmd : command_t;
   signal address : std_logic_vector(31 downto 0);
   signal cmd_size : positive;
-  signal ext_in  :  ext_socbridge_in_t;
+  signal ext_to_socbridge_driver  :  ext_to_socbridge_driver_t;
-  signal ext_out :  ext_socbridge_out_t;
+  signal socbridge_driver_to_ext :  socbridge_driver_to_ext_t;
-  signal int_in  :  int_socbridge_in_t;
+  signal buffer_to_socbridge_driver  :  buffer_to_socbridge_driver_t;
-  signal int_out :  int_socbridge_out_t;
+  signal socbridge_driver_to_buffer :  socbridge_driver_to_buffer_t;
-  signal ctrl_in :  controller_to_driver_t;
+  signal controller_to_socbridge_driver :  controller_to_socbridge_driver_t;
-  signal ctrl_out :  driver_to_controller_t;
+  signal socbridge_driver_controller :  socbridge_driver_to_controller_t;
-  signal curr_word : std_logic_vector(ext_in.payload'length - 1 downto 0);
+  signal curr_word : std_logic_vector(ext_to_socbridge_driver.payload'length - 1 downto 0);
-  signal expected_out : std_logic_vector(ext_out.payload'length - 1 downto 0);
+  signal expected_out : std_logic_vector(socbridge_driver_to_ext.payload'length - 1 downto 0);
   
   constant CLK_PERIOD : TIME := 10 ns;
   constant SIMULATION_CYCLE_COUNT : INTEGER := 100;
@@ -44,19 +44,19 @@ architecture tb of socbridge_driver_tb is
     end if;
   end procedure;
   
-  procedure check_data_out(correct_data: std_logic_vector(ext_out.payload'length - 1 downto 0)) is
+  procedure check_data_out(correct_data: std_logic_vector(socbridge_driver_to_ext.payload'length - 1 downto 0)) is
   begin
-    if(not (correct_data = ext_out.payload)) then
+    if(not (correct_data = socbridge_driver_to_ext.payload)) then
-      report "Data out is not what was expected, found " & to_string(ext_out.payload)
+      report "Data out is not what was expected, found " & to_string(socbridge_driver_to_ext.payload)
             & " but expected " & to_string(correct_data) severity error;
       fail("Data out");
     end if;
   end procedure;
 
-  procedure check_parity(correct_data: std_logic_vector(ext_out.payload'length - 1 downto 0)) is
+  procedure check_parity(correct_data: std_logic_vector(socbridge_driver_to_ext.payload'length - 1 downto 0)) is
   begin
-    if(not (calc_parity(correct_data) = calc_parity(ext_out.payload))) then
+    if(not (calc_parity(correct_data) = calc_parity(socbridge_driver_to_ext.payload))) then
-      report "Parity out is not what was expected, found " & std_logic'image(calc_parity(ext_out.payload))
+      report "Parity out is not what was expected, found " & std_logic'image(calc_parity(socbridge_driver_to_ext.payload))
             & " but expected " & std_logic'image(calc_parity(correct_data))  severity error;
       fail("Parity out");
     end if;
@@ -69,10 +69,10 @@ architecture tb of socbridge_driver_tb is
 --      cmd     : in command_t;
 --      address : in std_logic_vector(31 downto 0);
 --      cmd_size: in positive;
---      ext_in  : in ext_socbridge_in_t;
+--      ext_to_socbridge_driver  : in ext_to_socbridge_driver_t;
---      ext_out : out ext_socbridge_out_t;
+--      socbridge_driver_to_ext : out socbridge_driver_to_ext_t;
---      int_in  : out int_socbridge_in_t;
+--      buffer_to_socbridge_driver  : out buffer_to_socbridge_driver_t;
---      int_out : in int_socbridge_out_t
+--      socbridge_driver_to_buffer : in socbridge_driver_to_buffer_t
 --    );
 --  end component socbridge_driver;
 
@@ -81,15 +81,15 @@ begin
    port map(
       clk => clk,
       rst => rst,
-      ctrl_in => ctrl_in,
+      controller_to_socbridge_driver => controller_to_socbridge_driver,
-      ctrl_out => ctrl_out,
+      socbridge_driver_to_controller => socbridge_driver_controller,
-      ext_in => ext_in,
+      ext_to_socbridge_driver => ext_to_socbridge_driver,
-      ext_out => ext_out,
+      socbridge_driver_to_ext => socbridge_driver_to_ext,
-      int_in => int_in,
+      buffer_to_socbridge_driver => buffer_to_socbridge_driver,
-      int_out => int_out
+      socbridge_driver_to_buffer => socbridge_driver_to_buffer
   );
 
-  ext_in.control(1) <= clk;
+  ext_to_socbridge_driver.control(1) <= clk;
   real_clk_proc: process
   begin
     for x in 0 to SIMULATION_CYCLE_COUNT*2 loop
@@ -104,10 +104,10 @@ begin
   begin
     wait for CLK_PERIOD / 2;
     for x in 0 to SIMULATION_CYCLE_COUNT loop
-      if last_clk = ext_out.control(1) then
+      if last_clk = socbridge_driver_to_ext.control(1) then
         report "Secondary side clk not correct." severity error;
       end if;
-      last_clk := ext_out.control(1);
+      last_clk := socbridge_driver_to_ext.control(1);
       wait for CLK_PERIOD;
     end loop;
     wait;
@@ -254,8 +254,8 @@ begin
 
   external_stimulus_signal: process(curr_word)
   begin
-    ext_in.payload <= curr_word;
+    ext_to_socbridge_driver.payload <= curr_word;
-    ext_in.control(0) <= calc_parity(curr_word);
+    ext_to_socbridge_driver.control(0) <= calc_parity(curr_word);
   end process external_stimulus_signal;
 
   external_stimulus: process
@@ -299,30 +299,30 @@ begin
 
   internal_stimulus: process
   begin
-    int_in.is_full_in <= '0';
+    buffer_to_socbridge_driver.is_full_in <= '0';
-    int_in.write_enable_out <= '0';
+    buffer_to_socbridge_driver.write_enable_out <= '0';
     wait for 3 * CLK_PERIOD;
     -- stimulus goes here
-    int_in.write_enable_out <= '1';
+    buffer_to_socbridge_driver.write_enable_out <= '1';
-    int_in.payload <= "00000001";
+    buffer_to_socbridge_driver.payload <= "00000001";
-    wait until rising_edge(clk) and int_out.is_full_out = '0';
+    wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0';
     wait until falling_edge(clk);
-    int_in.payload <= "00000010";
+    buffer_to_socbridge_driver.payload <= "00000010";
-    wait until rising_edge(clk) and int_out.is_full_out = '0';
+    wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0';
     wait until falling_edge(clk);
-    int_in.payload <= "00000100";
+    buffer_to_socbridge_driver.payload <= "00000100";
-    wait until rising_edge(clk) and int_out.is_full_out = '0';
+    wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0';
     wait until falling_edge(clk);
-    int_in.payload <= "00001000";
+    buffer_to_socbridge_driver.payload <= "00001000";
-    wait until rising_edge(clk) and int_out.is_full_out = '0';
+    wait until rising_edge(clk) and socbridge_driver_to_buffer.is_full_out = '0';
     wait until falling_edge(clk);
-    int_in.payload <= "00010000";
+    buffer_to_socbridge_driver.payload <= "00010000";
-    wait until int_out.is_full_out = '0';
+    wait until socbridge_driver_to_buffer.is_full_out = '0';
     wait for CLK_PERIOD/2;
     wait until rising_edge(clk);
     wait until rising_edge(clk);
-    int_in.payload <= "00100000";
+    buffer_to_socbridge_driver.payload <= "00100000";
-    wait until int_out.is_full_out = '0';
+    wait until socbridge_driver_to_buffer.is_full_out = '0';
     wait for CLK_PERIOD/2;
     wait until rising_edge(clk);
     wait until rising_edge(clk); --- ??? Why all these rising_edge checks?

src/socbridge/socbridge_driver_tb_pkg.vhd

@@ -24,7 +24,7 @@ package socbridge_driver_tb_pkg is
   type translator_state_t is (IDLE, SEND, SEND_ACCEPTED, AWAIT);
 
   type translator_state_rec_t is record
-    curr_inst : controller_to_driver_t;
+    curr_inst : controller_to_socbridge_driver_t;
     curr_state : translator_state_t;
     is_first_word : std_logic;
   end record translator_state_rec_t; 
@@ -37,7 +37,7 @@ package socbridge_driver_tb_pkg is
 
   type state_rec_t is record
     curr_state: state_t;
-    ext_in_reg, ext_out_reg : ext_protocol_t; 
+    ext_to_socbridge_driver_reg, socbridge_driver_to_ext_reg : ext_protocol_t; 
     write_stage, read_stage : NATURAL;
     curr_cmd : command_t;
     curr_cmd_size: integer;
@@ -56,8 +56,8 @@ package socbridge_driver_tb_pkg is
   --- DEBUG GLOBAL SIGNALS ---
   -- synthesis translate_off 
   signal G_next_parity_out : std_logic;
-  signal G_ext_in_rec : ext_protocol_t;
+  signal G_ext_to_socbridge_driver_rec : ext_protocol_t;
-  signal G_ext_out_data_cmd : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
+  signal G_socbridge_driver_to_ext_data_cmd : std_logic_vector(interface_inst.socbridge.payload_width - 1 downto 0);
   signal G_next_state : state_t;
   signal G_curr_command : command_t;
   signal G_curr_command_bits : std_logic_vector(4 downto 0);