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testbench almost done, needs debugging

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Adam Magnusson 2025-02-28 17:03:13 +01:00 committed by Erik Örtenberg
parent 933e5b66bc
commit e7b4772223
2 changed files with 60 additions and 20 deletions
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18
src/control_unit.vhd
View File

@ -26,13 +26,13 @@ architecture behave of control_unit is
begin
comb_proc: process(control_in, control_out, state)
comb_proc: process(control_in, state)
variable ored: std_logic := '0';
begin
ready_reduction: for i in 0 to number_of_drivers loop
ored <= ored or control_in.active_driver(i);
ready_reduction: for i in 0 to number_of_drivers - 1 loop
ored := ored or control_in.active_driver(i);
end loop ready_reduction;
ready <= ored;
state.ready <= ored;
control_out.driver_id <= state.curr_driver;
control_out.address <= state.address;
control_out.seq_mem_access_count <= state.seq_mem_access_count;
@ -41,11 +41,11 @@ begin
sync_proc: process(clk, state)
begin
if rising_edge(clk) then
if rst = '0' then
state <= (others => '0',
others => '0',
others => '0',
'1');
if rst = '1' then
state <= ((others => '0'),
(others => '0'),
(others => '0'),
'0');
else
if state.ready = '1' then
state.address <= control_in.address;

62
src/control_unit_tb.vhd
View File

@ -4,15 +4,27 @@ use IEEE.MATH_REAL.all;
library work;
use work.io_types.all;
entity control_unit_tb
entity control_unit_tb is
end entity control_unit_tb;
architecture tb of control_unit_tb is
constant cycle := 10 ns;
signal clock := '0';
signal finished: std_logic;
constant cycle: Time := 10 ns;
signal clock: std_logic := '0';
signal stim_finished, mon_finished: std_logic;
signal reset: std_logic;
signal control_input: control_unit_in_t := (
(others => '0'),
(others => '0'),
(others => '0'),
(others => '0'));
signal control_output: control_unit_out_t := (
(others => '0'),
(others => '0'),
(others => '0'),
'0');
signal current_driver : std_logic_vector(2 downto 0) := "000";
shared variable word_counter: natural := 0;
component control_unit is
port(
@ -23,27 +35,55 @@ architecture tb of control_unit_tb is
begin
clock <= not clock after cycle / 2 when finished /= '1';
clock <= not clock after cycle / 2 when (stim_finished and mon_finished) /= '1';
control_unit_inst: control_unit
port map(
clk => clock,
rst => reset,
control_in => control_input,
control_out => control_output
);
stimulus_proc: process
begin
finished <= '0';
stim_finished <= '0';
wait for cycle;
control_input.driver_id <= "010";
control_input.active_driver <= "000";
control_input.address <= x"F0F0F0F0";
control_input.seq_mem_access_count <= "00000111";
finished <= '1';
report "entering loop with word_counter" & integer'image(word_counter);
for_loop: for i in word_counter - 1 downto 0 loop
wait for cycle;
report "word counter is " & integer'image(word_counter);
end loop for_loop;
control_input.active_driver <= "000";
stim_finished <= '1';
wait until mon_finished = '1';
wait;
end process stimulus_proc;
monitor_proc: process
begin
finished <= '0';
mon_finished <= '0';
finished <= '1';
wait for cycle;
wait for cycle;
assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity warning;
assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity warning;
wait until word_counter = 0;
assert control_output.ready = '1' report "control_unit did not signal ready" severity warning;
mon_finished <= '1';
wait until stim_finished = '1';
wait;
end process monitor_proc;
end architecture tb;