added initial driver file
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src/socbridge_driver.vhd
Normal file
24
src/socbridge_driver.vhd
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library IEEE;
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use IEEE.std_logic_1164.all;
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library work;
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use work.io_types.all;
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entity socbridge_driver is
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port(
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clk : in std_logic;
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reset : in std_logic;
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ext_in : in ext_socbridge_in_t;
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ext_out : out ext_socbridge_out_t;
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int_in : out int_socbridge_in_t;
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int_out : in int_socbridge_out_t
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);
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end entity socbridge_driver;
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architecture rtl of socbridge_driver is
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begin
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ext_out <= (payload => (others => '0'), control => (others => '0'));
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int_in <= (payload => (others => '0'), write_enable_in => '0', is_full_out =>'0');
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end architecture rtl;
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