fixed bug which occurs due to socbridge not handling addresses seperately for read and writes

src/socbridge/socbridge_driver.vhd

@@ -13,7 +13,8 @@ use grlib.stdlib.all;
 
 entity socbridge_driver is
   generic(
-    MAX_PKT_SIZE : integer range 1 to 128 := 8
+    MAX_PKT_SIZE : integer range 1 to 128 := 128;
+    BUFFER_SIZE : integer
          );
   port(
     clk                            : in std_logic;
@@ -341,7 +342,7 @@ begin
         elsif st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD
         or st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
           trans_read_next_state <= IDLE;
-        elsif trans_st.read.curr_inst.request = '1' then
+        elsif trans_st.read.curr_inst.request = '1' and BUFFER_SIZE - ip_to_socbridge_driver.read_fifo.used_slots > 2*MAX_PKT_SIZE then
           trans_read_next_state <= SEND;
         else 
           trans_read_next_state <= IDLE;
@@ -362,7 +363,7 @@ begin
           trans_read_next_state <= IDLE;
         elsif ip_to_socbridge_driver.flush = '1'and not st.read_in_flight then
           trans_read_next_state <= IDLE;
-        elsif not st.read_in_flight then
+        elsif not st.read_in_flight and BUFFER_SIZE - ip_to_socbridge_driver.read_fifo.used_slots > 2*MAX_PKT_SIZE then
           trans_read_next_state <= SEND;
         else 
           trans_read_next_state <= AWAIT;
@@ -393,7 +394,7 @@ begin
       else 
         next_tx_data_size <= 0;
       end if;
-    elsif trans_st.write.curr_state = SEND then
+    elsif trans_st.write.curr_state = SEND and not st.read_in_flight then
       if trans_st.write.is_first_word = '1' then 
         local_next_tx_transaction := WRITE_ADD;
       else
@@ -616,6 +617,14 @@ begin
           end if;
           trans_st.write.is_first_word <= '1';
         when SEND =>
+          if trans_st.write.curr_inst.seq_mem_access_count mod 256 = 0 then
+            trans_st.write.is_first_word <= '1';
+          elsif st.last_sent_transaction = READ or st.last_sent_transaction = READ_ADD 
+          or next_tx_transaction = READ or next_tx_transaction = READ_ADD then
+            trans_st.write.is_first_word <= '1';
+          else 
+            trans_st.write.is_first_word <= '0';
+          end if;
         when SEND_ACCEPTED => 
           trans_st.write.curr_inst.seq_mem_access_count <= trans_st.write.curr_inst.seq_mem_access_count - MAX_PKT_SIZE;
           trans_st.write.curr_inst.address <= std_logic_vector(unsigned(trans_st.write.curr_inst.address) + MAX_PKT_SIZE);