example library package assuming vhdl08. Can be chagned to older ver if needed

Reviewed-on: #6

scripts/build_env.py

@@ -2,7 +2,10 @@ import os
 from re import split
 import subprocess
 
-def ghdlEnvExists(relativePath="work"):
+def getCfFileId(std: str):
+    return "08" if std == "08" else "93" ## Weird behaviour from GHDL, but all vhdl versions besides 08 have [...]93.cf
+
+def ghdlEnvExists(std, relativePath="work"):
     ## Check if work exists
     try:
         os.lstat(relativePath)
@@ -14,34 +17,36 @@ def ghdlEnvExists(relativePath="work"):
         return False
     cfFileExists = False
     filesInWork = os.listdir(relativePath)
+    cfFileId = getCfFileId(std)
     for file in filesInWork:
-        if ".cf" in file:
+        if ".cf" in file and cfFileId in file:
             cfFileExists = True
     if not cfFileExists:
         return False
     ## Nothing bad, continue
     return True
 
-def createBuildEnv():
-    if ghdlEnvExists():
+def createBuildEnv(std: str):
+    if ghdlEnvExists(std=std):
         print("Build environment already exists, exiting...")
         return -1
     ## Create build env
     print("Initializing GHDL project in current directory...")
     os.makedirs("work",exist_ok=True)
-    addAllVHDLFiles(init=True)
+    addAllVHDLFiles(std=std, init=True)
     return 0
 
-def addAllVHDLFiles(init=False):
+def addAllVHDLFiles(std: str, init=False):
     ## Ensure everything is ready for adding files 
     ## (init exception to avoid one if-case in ghdlEnvExists)
-    if not ghdlEnvExists() and not init:
+    if not ghdlEnvExists(std=std) and not init:
        return -1
     vhdlFiles = []
     currentlyAdded = []
+    cfFileId = getCfFileId(std)
     ## Find already present files
     if not init:
-        cfFileName = list(filter(lambda x: ".cf" in x, os.listdir("work")))[0]
+        cfFileName = list(filter(lambda x: ".cf" in x and cfFileId in x, os.listdir("work")))[0]
         cfFilePath = os.path.join(os.getcwd(),f"work/{cfFileName}")
         currentlyAdded = getCurrentlyAddedFiles(cfFilePath)
     ## Add files not added
@@ -50,7 +55,7 @@ def addAllVHDLFiles(init=False):
             vhdlFiles.append(file)
     if len(vhdlFiles) > 0:
         print(f"Detected new files. Adding {vhdlFiles}")
-        command = ["ghdl", "-i", "--workdir=work"] + vhdlFiles
+        command = ["ghdl", "-i", "--workdir=work", "--work=work", f"--std={std}"] + vhdlFiles
         subprocess.run(command)
     return 0
 
@@ -61,7 +66,3 @@ def getCurrentlyAddedFiles(cfFilePath:str):
     fileLines = filter(lambda x: "file" in x, lines) 
     files = map(lambda x: split("\" \"",x)[1], fileLines)
     return list(files)
-
-
-if __name__ == "__main__":
-    getCurrentlyAddedFiles("work/work-obj93.cf")

scripts/elab.py

@@ -4,7 +4,7 @@ import build_env
 
 def elabDesign(topDef: str, arch: str, lib: str, std: str):
     ## Add all source files present in pwd
-    if build_env.addAllVHDLFiles() == -1:
+    if build_env.addAllVHDLFiles(std) == -1:
         print("Adding files failed. GHDL Build environment may be broken...")
         return -1
     command = [
@@ -18,7 +18,6 @@ def runDesign(topDef: str, arch: str, lib: str, std: str):
         print("Elaboration failed...")
         return -1
     os.makedirs("wave",exist_ok=True)
-    libPath = os.path.join(os.getcwd(), lib)
     wavePath = os.path.join(os.getcwd(), "wave")
     command = [ ## may add -v for verbose
         "ghdl", "--elab-run", f"--workdir={lib}", f"--work={lib}", f"--std={std}",

scripts/gantry.py

@@ -11,15 +11,17 @@ hardware = typer.Typer()
 app.add_typer(software, name="sim", help="GHDL simulator command group")
 app.add_typer(hardware, name="syn", help="Synthesis and deployment command group")
 
-
-@software.command(help="Initializes the GHDL build environment in a library named \"work\". Adds all files ending in \".vhd\" to the project")
-def init():
-    return build_env.createBuildEnv()
-
-
 def complete_vhdl_ver():
     return ["87", "93", "93c", "00", "02", "08"]
 
+
+@software.command(help="Initializes the GHDL build environment in a library named \"work\". Adds all files ending in \".vhd\" to the project")
+def init(
+        std: Annotated[str, typer.Option(help="Which VHDL standard to use. 87, 93, 93c, 00, 02 or 08", autocompletion=complete_vhdl_ver)] = "93c"
+        ):
+    return build_env.createBuildEnv(std)
+
+
 @software.command(help="Runs analysis and elaboration on the provided top definition and architecture using GHDL. Automatically adds new files not present in the project")
 def elab(
         topdef: Annotated[str, typer.Argument(help="Top Definition entity to synthesize")] = "",

src/io_type_pkg.vhd

@@ -0,0 +1,67 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+
+package io_types is
+
+  --- STANDARD TYPES ---
+  type ext_protocol_impl_t is record 
+    payload, control: STD_LOGIC_VECTOR;
+  end record ext_protocol_impl_t;
+
+  type int_protocol_impl_t is record
+    payload : STD_LOGIC_VECTOR;
+  -- ADD MORE STUFF WHEN WE HAVE DECIDED UPON DRIVER INTERFACE
+  end record int_protocol_impl_t;
+
+  type ext_protocol_def_t is record
+    name: string (1 to 20);
+    payload_width: natural;
+    control_width_in, control_width_out: natural;
+  end record ext_protocol_def_t;
+
+  type interface_inst_t is record
+    socbridge: ext_protocol_def_t;
+    spi: ext_protocol_def_t;
+  end record interface_inst_t;
+
+  --- PROTOCOL INFORMATION ---
+  constant interface_inst : interface_inst_t := (
+    ("SoCBridge           ", 8, 2, 2),
+    ("SPI                 ", 1, 3, 3)
+  ); 
+
+  --- AUTOGENERATED TYPES ---
+  type ext_interface_in_t is record
+    socbridge : ext_protocol_impl_t( 
+      payload(interface_inst.socbridge.payload_width - 1 downto 0),
+      control(interface_inst.socbridge.control_width_in - 1 downto 0));
+    spi : ext_protocol_impl_t(
+      payload(interface_inst.spi.payload_width - 1 downto 0),
+      control(interface_inst.spi.control_width_in - 1 downto 0));
+  end record ext_interface_in_t;
+
+  type ext_interface_out_t is record
+    socbridge : ext_protocol_impl_t( 
+      payload(interface_inst.socbridge.payload_width - 1 downto 0),
+      control(interface_inst.socbridge.control_width_out - 1 downto 0));
+    spi : ext_protocol_impl_t(
+      payload(interface_inst.spi.payload_width - 1 downto 0),
+      control(interface_inst.spi.control_width_out - 1 downto 0));
+  end record ext_interface_out_t;
+
+  type int_interface_in_t is record
+    socbridge : int_protocol_impl_t(
+      payload(interface_inst.socbridge.payload_width - 1 downto 0));
+    spi : int_protocol_impl_t(
+      payload(interface_inst.spi.payload_width - 1 downto 0));
+  end record int_interface_in_t;
+
+  type int_interface_out_t is record
+    socbridge : int_protocol_impl_t(
+      payload(interface_inst.socbridge.payload_width - 1 downto 0));
+    spi : int_protocol_impl_t(
+      payload(interface_inst.spi.payload_width - 1 downto 0));
+  end record int_interface_out_t;
+
+end package io_types;

src/test.vhd

@@ -0,0 +1,27 @@
+library IEEE;
+library work;
+use work.io_types.all;
+
+entity test is
+  port (
+    ext_interface_in    : in ext_interface_in_t;
+    ext_interface_out   : out ext_interface_out_t
+  );
+end entity test;
+
+architecture rtl of test is
+  signal int_interface_in  : int_interface_in_t;
+  signal int_interface_out : int_interface_out_t;
+begin
+  
+  proc_name: process
+  begin
+    
+  report "Hello";
+  report integer'image(ext_interface_in.socbridge.payload'length);
+  report integer'image(ext_interface_in.spi.payload'length);
+  wait;
+  end process proc_name;
+  
+  
+end architecture rtl;