ganimede-multipacket #19
@ -287,17 +287,17 @@ begin
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when RX_W_BODY =>
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if st.rx_stage mod 4 = 0 and st.rx_stage /= st.rx_data_size then
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socbridge_driver_to_manager.data <= st.curr_write_data;
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socbridge_driver_to_manager.address <= st.curr_rx_write_addr;
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socbridge_driver_to_manager.address <= st.manager_addr;
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socbridge_driver_to_manager.valid <= '1';
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end if;
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when RX_R_BODY =>
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when RX_AWAIT =>
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if st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD then
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socbridge_driver_to_manager.data <= st.curr_write_data;
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socbridge_driver_to_manager.address <= st.curr_rx_write_addr;
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socbridge_driver_to_manager.address <= st.manager_addr;
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socbridge_driver_to_manager.valid <= '1';
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else
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socbridge_driver_to_manager.address <= st.curr_rx_read_addr;
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socbridge_driver_to_manager.address <= st.manager_addr;
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end if;
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when ADDR1 =>
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when ADDR2 =>
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@ -438,8 +438,7 @@ begin
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st.curr_rx_transaction <= NO_OP;
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st.tx_data_size <= 0;
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st.rx_data_size <= 0;
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st.curr_rx_read_addr <= (others => '0');
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st.curr_rx_write_addr <= (others => '0');
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st.manager_addr <= (others => '0');
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st.curr_write_data <= (others => '0');
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st.curr_read_data <= (others => '0');
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socbridge_driver_to_ip.data <= (others => '0');
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@ -450,8 +449,8 @@ begin
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elsif(rising_edge(ext_to_socbridge_driver_rec.clk)) then
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st.ext_to_socbridge_driver_reg.data <= ext_to_socbridge_driver_rec.data;
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st.ext_to_socbridge_driver_reg.clk <= ext_to_socbridge_driver_rec.clk;
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st.ext_to_socbridge_driver_reg.parity <= ext_to_socbridge_driver_rec.parity;
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-- PARITY CHECK NOT IMPLEMENTED, REMOVING
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--st.ext_to_socbridge_driver_reg.parity <= ext_to_socbridge_driver_rec.parity;
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st.socbridge_driver_to_ext_reg.data <= next_data_out;
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st.socbridge_driver_to_ext_reg.clk <= not st.socbridge_driver_to_ext_reg.clk;
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st.socbridge_driver_to_ext_reg.parity <= next_parity_out;
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@ -558,41 +557,41 @@ begin
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st.curr_write_data((((st.rx_stage - 1) mod 4) + 1) * 8 - 1 downto ((((st.rx_stage - 1) mod 4) + 1) - 1) * 8) <= st.ext_to_socbridge_driver_reg.data;
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end if;
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if (st.rx_stage - 2) mod 4 = 0 and st.rx_data_size - st.rx_stage > 4 then
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st.curr_rx_write_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_write_addr) + 4), 32));
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st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32));
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end if;
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when RX_AWAIT =>
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st.curr_read_data <= manager_to_socbridge_driver.data;
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-- THIS DOESN'T WORK FOR LARGER THAN 4 BYTE ACCESSES, SHOULD BE FIXED BUT NOT NEEDED IF ONLY 4 BYTE ACCESSES ARRIVE
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if st.curr_tx_transaction = READ_RESPONSE or st.curr_tx_transaction = WRITE_ACK then
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if (st.curr_rx_transaction = READ or st.curr_rx_transaction = READ_ADD) and (st.tx_stage - 2) mod 4 = 0 then
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st.curr_rx_read_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_read_addr) + 4), 32));
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st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32));
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elsif (st.curr_rx_transaction = WRITE or st.curr_rx_transaction = WRITE_ADD) and (st.rx_stage - 2) mod 4 = 0 then
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st.curr_rx_write_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.curr_rx_write_addr) + 4), 32));
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st.manager_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(st.manager_addr) + 4), 32));
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end if;
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end if;
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when ADDR1 =>
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if st.curr_rx_transaction = READ_ADD then
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st.curr_rx_read_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
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st.manager_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
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else
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st.curr_rx_write_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
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st.manager_addr(31 downto 24) <= st.ext_to_socbridge_driver_reg.data;
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end if;
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when ADDR2 =>
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if st.curr_rx_transaction = READ_ADD then
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st.curr_rx_read_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
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st.manager_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
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else
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st.curr_rx_write_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
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st.manager_addr(23 downto 16) <= st.ext_to_socbridge_driver_reg.data;
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end if;
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when ADDR3 =>
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if st.curr_rx_transaction = READ_ADD then
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st.curr_rx_read_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
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st.manager_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
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else
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st.curr_rx_write_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
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st.manager_addr(15 downto 8) <= st.ext_to_socbridge_driver_reg.data;
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end if;
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when ADDR4 =>
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if st.curr_rx_transaction = READ_ADD then
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st.curr_rx_read_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
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st.manager_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
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else
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st.curr_rx_write_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
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st.manager_addr(7 downto 0) <= st.ext_to_socbridge_driver_reg.data;
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end if;
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when others =>
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end case;
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@ -51,8 +51,7 @@ package socbridge_driver_pkg is
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curr_write_data : std_logic_vector(31 downto 0);
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curr_read_data : std_logic_vector(31 downto 0);
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curr_tx_addr : std_logic_vector(31 downto 0);
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curr_rx_read_addr : std_logic_vector(31 downto 0);
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curr_rx_write_addr : std_logic_vector(31 downto 0);
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manager_addr : std_logic_vector(31 downto 0);
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read_in_flight : boolean;
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write_in_flight : boolean;
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last_sent_transaction : transaction_t;
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