src/control_unit.vhd

@@ -0,0 +1,66 @@
+library IEEE;  
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+library work;
+use work.io_types.all;
+
+entity control_unit is
+  
+  port (
+    clk, rst: in std_logic;
+    control_in: in control_unit_in_t;
+    control_out: out control_unit_out_t
+  );
+
+end entity control_unit;
+
+architecture behave of control_unit is
+  type state_t is record
+    address: std_logic_vector(address_width - 1 downto 0);
+    seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
+    curr_driver: std_logic_vector(number_of_drivers - 1 downto 0); --one-hot encoded, 0 means disabled
+    ready: std_logic;
+    instruction: std_logic_vector(inst_word_width - 1 downto 0);
+  end record state_t;
+
+  signal state: state_t;
+  shared variable ored: std_logic;
+  
+
+begin
+
+  comb_proc: process(control_in, state)
+  begin
+    ored := '0';
+    ready_reduction: for i in 0 to number_of_drivers - 1 loop
+      ored := ored or control_in.active_driver(i);
+    end loop ready_reduction;
+    control_out.driver_id <= state.curr_driver;
+    control_out.address <= state.address;
+    control_out.seq_mem_access_count <= state.seq_mem_access_count;        
+    control_out.ready <= state.ready;
+    control_out.instruction <= state.instruction;
+  end process comb_proc;
+
+  sync_proc: process(clk, state)
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        state <= ((others => '0'), 
+                  (others => '0'), 
+                  (others => '0'),
+                  '1',
+                  x"00");
+      else
+        state.ready <= not ored;
+        if ored = '0' then
+          state.address <= control_in.address;
+          state.seq_mem_access_count <= control_in.seq_mem_access_count;
+          state.curr_driver <= control_in.driver_id;
+          state.instruction <= control_in.instruction;
+        end if;
+      end if;
+    end if;
+  end process sync_proc;
+  
+end architecture behave;

src/control_unit_tb.vhd

@@ -0,0 +1,91 @@
+library IEEE;  
+use IEEE.std_logic_1164.all;
+use IEEE.MATH_REAL.all;
+use ieee.numeric_std.all;
+library work;
+use work.io_types.all;
+
+entity control_unit_tb is
+end entity control_unit_tb;
+
+architecture tb of control_unit_tb is
+
+  constant cycle: Time := 10 ns;
+  signal clock: std_logic := '0';
+  signal reset: std_logic := '0';
+  signal control_input: control_unit_in_t := (
+                                              (others => '0'),
+                                              (others => '0'),
+                                              (others => '0'),
+                                              (others => '0'),
+                                              x"00");
+  signal control_output: control_unit_out_t := (
+                                              (others => '0'),
+                                              (others => '0'),
+                                              (others => '1'),
+                                              '1',
+                                              x"00");
+  signal current_driver : std_logic_vector(2 downto 0) := "000";
+  shared variable word_counter: natural := 0;
+
+begin
+  
+  clock_proc: process
+  begin
+  for i in 0 to 50 loop
+    wait for cycle / 2;
+    clock <= not clock;
+  end loop;
+  wait;
+  end process clock_proc;
+
+  control_unit_inst: entity work.control_unit
+    port map(
+      clk => clock,
+      rst => reset,
+      control_in => control_input,
+      control_out => control_output
+    );
+
+stimulus_proc: process
+begin
+  wait for cycle;
+
+  control_input.driver_id <= "010";
+  control_input.active_driver <= "000";
+  control_input.address <= x"F0F0F0F0";
+  control_input.seq_mem_access_count <= "00000011";
+  control_input.instruction <= x"81";
+  word_counter := 3;
+  wait for cycle;
+  current_driver <= "010";
+  
+  report "entering loop with word_counter" & integer'image(word_counter);
+  for_loop: for i in word_counter - 1 downto 0 loop
+    wait for cycle;
+    report "words remaining are " & integer'image(i);
+  end loop for_loop;
+  
+  control_input.active_driver <= "000";
+  report "Stim process done";
+  wait;
+end process stimulus_proc; 
+
+monitor_proc: process
+begin
+
+  wait for cycle;
+
+  wait for cycle;
+  assert control_output.driver_id = "010" report "Incorrect driver_id from control_unit" severity error;
+  assert control_output.address = x"F0F0F0F0" report "Incorrect address from control_unit" severity error;
+  assert control_output.instruction = x"81" report "Incorrect memory op from control_unit" severity error;
+
+  wait for 5 * cycle;
+  reset <= '1';
+
+  report "Monitor process done";
+  wait;
+end process monitor_proc;
+
+end architecture tb;

src/io_type_pkg.vhd

@@ -15,6 +15,25 @@ package io_types is
     socbridge: ext_protocol_def_t;
   end record interface_inst_t;
 
+  constant number_of_drivers: natural := 3;
+  constant address_width: natural := 32;
+  constant seq_vector_length: natural := 8;
+  constant inst_word_width: natural := 8;
+
+  type control_unit_out_t is record
+    driver_id: std_logic_vector(number_of_drivers - 1 downto 0);
+    address: std_logic_vector(address_width - 1 downto 0);
+    seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
+    ready: std_logic;
+    instruction: std_logic_vector(inst_word_width - 1 downto 0);
+  end record control_unit_out_t;
+
+  type control_unit_in_t is record
+    driver_id, active_driver: std_logic_vector(number_of_drivers - 1 downto 0);
+    address: std_logic_vector(address_width - 1 downto 0);
+    seq_mem_access_count: std_logic_vector(seq_vector_length - 1 downto 0);
+    instruction: std_logic_vector(inst_word_width - 1 downto 0);
+  end record control_unit_in_t;
   --- PROTOCOL INFORMATION ---
   constant interface_inst : interface_inst_t := (
     socbridge => ("SoCBridge           ", 8, 2, 2)