94 lines
2.6 KiB
VHDL
94 lines
2.6 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.NUMERIC_STD.all;
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library ganimede;
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use ganimede.io_types.all;
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library socbridge;
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use socbridge.socbridge_driver_tb_pkg.all;
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library controller;
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entity control_socbridge_tb is
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end entity control_socbridge_tb;
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architecture tb of control_socbridge_tb is
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constant cycle : Time := 10 ns;
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signal clk, rst : std_logic;
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signal cu_to_sb_cmd: command_t;
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signal cu_to_sb_address: std_logic_vector(31 downto 0);
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signal cmd_size : positive;
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signal ext_socbridge_in : ext_socbridge_in_t := (
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payload => (others => '0'),
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control => (others => '0')
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);
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signal ext_socbridge_out : ext_socbridge_out_t;
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signal int_socbridge_out : int_socbridge_out_t;
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signal int_socbridge_in : int_socbridge_in_t := (
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payload => (others => '0'),
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write_enable_out => '0',
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is_full_in => '0'
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);
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signal ext_control_input: ext_control_unit_in_t := (
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driver_id => (others => '0'),
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address => (others => '0'),
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seq_mem_access_count => 0,
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cmd => x"00"
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);
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signal int_control_input: int_control_unit_in_t := (active_driver => (others => '0'));
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signal ext_control_output: ext_control_unit_out_t;
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signal int_control_output: int_control_unit_out_t;
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signal driver_to_control: driver_to_control_t;
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signal control_to_driver: control_to_driver_t;
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begin
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socbridge_inst: entity socbridge.socbridge_driver
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port map(
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clk => clk,
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rst => rst,
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ctrl_in => control_to_driver,
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ctrl_out => driver_to_control,
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ext_in => ext_socbridge_in,
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ext_out => ext_socbridge_out,
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int_in => int_socbridge_in,
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int_out => int_socbridge_out
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);
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control_unit_inst: entity controller.control_unit
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port map(
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clk => clk,
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rst => rst,
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ext_control_in => ext_control_input,
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ext_control_out => ext_control_output,
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int_control_in => int_control_input,
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int_control_out => int_control_output
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);
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control_to_driver.address <= int_control_output.address;
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control_to_driver.request <= int_control_output.driver_id(0);
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control_to_driver.instruction <= int_control_output.instruction;
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control_to_driver.seq_mem_access_count <= int_control_output.seq_mem_access_count;
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int_control_input.active_driver(0) <= driver_to_control.is_active;
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clock_proc: process
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begin
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for i in 0 to 50 loop
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wait for cycle / 2;
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clk <= not clk;
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end loop;
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wait;
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end process clock_proc;
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stimulus_proc: process
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begin
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end process stimulus_proc;
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monitor_proc: process
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begin
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end process monitor_proc;
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end architecture tb;
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