41 lines
953 B
VHDL
41 lines
953 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity dummy_ip is
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port (
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clk, rst : in std_logic;
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ready_in, valid_in : in std_logic;
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ready_out, valid_out : out std_logic;
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data_in : in std_logic_vector(8 - 1 downto 0);
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data_out : out std_logic_vector(8 - 1 downto 0)
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);
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end entity dummy_ip;
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architecture rtl of dummy_ip is
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signal incremented_in : std_logic_vector(8 - 1 downto 0);
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begin
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comb_proc: process(ready_in, valid_in, data_in, incremented_in)
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begin
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ready_out <= ready_in;
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end process;
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seq_proc: process(clk,rst)
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begin
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if rst = '1' then
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valid_out <= '0';
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data_out <= (others => '0');
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elsif rising_edge(clk) then
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if valid_in = '1' and ready_in = '1' then
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valid_out <= '1';
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data_out <= std_logic_vector(unsigned(data_in) + 1);
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else
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valid_out <= '0';
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end if;
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elsif falling_edge(clk) then
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end if;
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end process seq_proc;
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end architecture rtl;
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