75 lines
2.2 KiB
VHDL
75 lines
2.2 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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library work;
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use work.io_types.all;
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entity ganimede is
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port (
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clk : in std_logic;
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reset : in std_logic;
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ext_interface_in : in ext_interface_in_t;
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ext_interface_out : out ext_interface_out_t;
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int_interface_in : in int_interface_in_t;
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int_interface_out : out int_interface_out_t
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);
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end entity ganimede;
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architecture rtl of ganimede is
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--- SIGNAL DECLERATIONS ---
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signal gan_int_interface_in : int_interface_in_t;
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signal gan_int_interface_out : int_interface_out_t;
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signal gan_ext_interface_in : ext_interface_in_t;
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signal gan_ext_interface_out : ext_interface_out_t;
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--signal gan_socbridge_WE_in : std_logic;
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--signal gan_socbridge_WE_out : std_logic;
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--signal gan_socbridge_is_full_in : std_logic;
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--signal gan_socbridge_is_full_out : std_logic;
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--- COMPONENT DECLERATIONS ---
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--component fifo is
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-- generic(
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-- WIDTH : positive;
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-- DEPTH : positive
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-- );
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-- port(
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-- clk, reset, read_enable, write_enable : in std_logic;
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-- is_full, is_empty : out std_logic;
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-- data_in : in std_logic_vector(WIDTH - 1 downto 0);
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-- data_out : out std_logic_vector(WIDTH - 1 downto 0)
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-- );
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--end component;
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component socbridge_driver is
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port(
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clk : in std_logic;
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reset : in std_logic;
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ext_in : in ext_socbridge_in_t;
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ext_out : out ext_socbridge_out_t;
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int_in : out int_socbridge_in_t;
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int_out : in int_socbridge_out_t
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);
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end component;
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begin
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--- CONNECT EXTERNAL SIGNALS TO INTERNAL CONNECTIONS ---
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gan_int_interface_in <= int_interface_in;
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int_interface_out <= gan_int_interface_out;
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gan_ext_interface_in <= ext_interface_in;
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ext_interface_out <= gan_ext_interface_out;
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--- DRIVER INSTANTIATION ---
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socbridge_driver_inst: socbridge_driver
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port map(
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clk => clk,
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reset => reset,
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ext_in => gan_ext_interface_in.socbridge,
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ext_out => gan_ext_interface_out.socbridge,
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int_in => gan_int_interface_in.socbridge,
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int_out => gan_int_interface_out.socbridge
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);
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--- LATER WE ADD OPTIMIZATIONS HERE ---
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end architecture rtl;
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