83 lines
2.9 KiB
VHDL
83 lines
2.9 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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library ganimede;
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use ganimede.io_types.all;
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library gan_socbridge;
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use gan_socbridge.socbridge_driver_tb_pkg.all;
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library controller;
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entity ganimede_toplevel is
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port (
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clk : in std_logic;
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rst : in std_logic;
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manager_to_ganimede : in manager_to_controller_t;
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ganimede_to_manager : out controller_to_manager_t;
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ext_to_ganimede : in ext_to_ganimede_t;
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ganimede_to_ext : out ganimede_to_ext_t;
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ip_to_ganimede : in ip_to_ganimede_t;
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ganimede_to_ip : out ganimede_to_ip_t
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);
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end entity ganimede_toplevel;
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architecture rtl of ganimede_toplevel is
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--- SIGNAL DECLERATIONS ---
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signal ext_to_drivers : ext_to_ganimede_t;
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signal drivers_to_ext : ganimede_to_ext_t;
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signal drivers_to_ip : ganimede_to_ip_t;
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signal ip_to_drivers : ip_to_ganimede_t;
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signal drivers_to_controller : drivers_to_controller_t;
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signal controller_to_drivers : controller_to_drivers_t;
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--signal gan_socbridge_WE_in : std_logic;
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--signal gan_socbridge_WE_out : std_logic;
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--signal gan_socbridge_is_full_in : std_logic;
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--signal gan_socbridge_is_full_out : std_logic;
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--- COMPONENT DECLERATIONS ---
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--component fifo is
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-- generic(
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-- WIDTH : positive;
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-- DEPTH : positive
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-- );
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-- port(
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-- clk, reset, read_enable, write_enable : in std_logic;
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-- is_full, is_empty : out std_logic;
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-- data_in : in std_logic_vector(WIDTH - 1 downto 0);
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-- data_out : out std_logic_vector(WIDTH - 1 downto 0)
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-- );
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--end component;
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begin
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--- CONNECT EXTERNAL SIGNALS TO INTERNAL CONNECTIONS ---
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ip_to_drivers <= ip_to_ganimede;
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ganimede_to_ip <= drivers_to_ip;
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ext_to_drivers <= ext_to_ganimede;
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ganimede_to_ext <= drivers_to_ext;
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--- DRIVER INSTANTIATION ---
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socbridge_inst: entity gan_socbridge.socbridge_driver
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port map(
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clk => clk,
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rst => rst,
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controller_to_socbridge_driver => controller_to_drivers.socbridge,
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socbridge_driver_to_controller => drivers_to_controller.socbridge,
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ext_to_socbridge_driver => ext_to_ganimede.socbridge,
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socbridge_driver_to_ext => ganimede_to_ext.socbridge,
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ip_to_socbridge_driver => ip_to_ganimede.socbridge,
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socbridge_driver_to_ip => ganimede_to_ip.socbridge
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);
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controller_unit_inst: entity controller.control_unit
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port map(
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clk => clk,
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rst => rst,
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manager_to_controller => manager_to_ganimede,
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controller_to_manager => ganimede_to_manager,
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drivers_to_controller => drivers_to_controller,
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controller_to_drivers => controller_to_drivers
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);
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--- LATER WE ADD OPTIMIZATIONS HERE ---
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end architecture rtl;
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