75 lines
2.0 KiB
VHDL
75 lines
2.0 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.MATH_REAL.all;
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use ieee.numeric_std.all;
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entity fifo_deserializer is
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generic (
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output_width : natural := 8;
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input_width : natural := 8;
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endianess : integer := 0 -- 0: little endian, 1: big endian
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);
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port (
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rst, clk : in std_logic;
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ready_in : in std_logic;
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ready_out : out std_logic;
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valid_in : in std_logic;
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valid_out : out std_logic;
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data_in : in std_logic_vector(input_width - 1 downto 0);
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data_out : out std_logic_vector(output_width - 1 downto 0)
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);
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end entity fifo_deserializer;
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architecture rtl of fifo_deserializer is
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constant out_over_in : natural := output_width / input_width - 1;
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type state_t is record
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count : integer;
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data : std_logic_vector(output_width - 1 downto 0);
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full_word : std_logic;
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prev_ready : std_logic;
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end record state_t;
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signal st : state_t;
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begin
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comb_proc: process(rst,clk,valid_in,ready_in,data_in,st)
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begin
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if st.full_word = '1' and ready_in = '1' then
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valid_out <= '1';
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else
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valid_out <= '0';
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end if;
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ready_out <= ready_in;
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data_out <= st.data;
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end process comb_proc;
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seq_proc: process(clk, rst)
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begin
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if rst = '1' then
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st.count <= 0;
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st.data <= (others => '0');
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st.full_word <= '0';
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st.prev_ready <= '0';
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elsif (rising_edge(clk)) then
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st.prev_ready <= ready_in;
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if valid_in = '1' and st.prev_ready = '1' then
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if endianess = 0 then
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st.data((out_over_in + 1 - st.count) * input_width - 1 downto (out_over_in - st.count) * input_width) <= data_in;
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else
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st.data((st.count + 1) * input_width - 1 downto st.count * input_width) <= data_in;
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end if;
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end if;
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if st.full_word = '1' and ready_in = '1' then
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st.full_word <= '0';
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end if;
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if st.count = out_over_in and valid_in = '1' then
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st.full_word <= '1';
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st.count <= 0;
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elsif valid_in = '1' then
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st.count <= st.count + 1;
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end if;
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end if;
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end process seq_proc;
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end architecture rtl;
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