33 lines
701 B
VHDL
33 lines
701 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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library work;
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use work.io_types.all;
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entity ganimede is
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port (
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ext_interface_in : in ext_interface_in_t;
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ext_interface_out : out ext_interface_out_t
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);
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end entity ganimede;
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architecture rtl of ganimede is
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--- SIGNALS INTERFACING THE IP CORE
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signal int_interface_in : int_interface_in_t;
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signal int_interface_out : int_interface_out_t;
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--- COMPONENT DECLERATIONS ---
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component socbridge_driver is
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port(
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ext_in : in ext_socbridge_in_t;
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ext_out : out ext_socbridge_out_t;
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int_in : in int_socbridge_in_t;
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int_out : out int_socbridge_out_t
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);
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end component;
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begin
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end architecture rtl;
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