50 lines
850 B
VHDL
50 lines
850 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.MATH_REAL.all;
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library work;
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use work.io_types.all;
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entity control_unit_tb
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end entity control_unit_tb;
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architecture tb of control_unit_tb is
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constant cycle := 10 ns;
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signal clock := '0';
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signal finished: std_logic;
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component control_unit is
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port(
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clk, rst: in std_logic;
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control_in: in control_unit_in_t;
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control_out: out control_unit_out_t);
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end component control_unit;
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begin
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clock <= not clock after cycle / 2 when finished /= '1';
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control_unit_inst: control_unit
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port map(
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clk => clock,
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rst => reset,
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);
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stimulus_proc: process
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begin
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finished <= '0';
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finished <= '1';
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end process stimulus_proc;
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monitor_proc: process
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begin
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finished <= '0';
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finished <= '1';
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end process monitor_proc;
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end architecture tb;
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