108 lines
3.7 KiB
VHDL
108 lines
3.7 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use ieee.numeric_std.all;
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use IEEE.MATH_REAL.all;
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library gan_ganimede;
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use gan_ganimede.io_types.all;
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library gan_socbridge;
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entity socbridge_driver_tb is
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end entity socbridge_driver_tb;
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architecture tb of socbridge_driver_tb is
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signal clk : std_logic := '0';
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signal rst : std_logic;
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signal ext_to_socbridge_driver : ext_to_socbridge_driver_t;
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signal socbridge_driver_to_ext : socbridge_driver_to_ext_t;
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signal ip_to_socbridge_driver : ip_to_socbridge_driver_t;
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signal socbridge_driver_to_ip : socbridge_driver_to_ip_t;
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signal controller_to_socbridge_driver : controller_to_socbridge_driver_t;
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signal socbridge_driver_to_controller : socbridge_driver_to_controller_t;
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shared variable done : boolean := FALSE;
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constant CLK_PERIOD : TIME := 10 ns;
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constant MAX_CYCLE_COUNT : INTEGER := 1000000;
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begin
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socbridge_driver_inst: entity gan_socbridge.socbridge_driver
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port map(
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clk => clk,
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rst => rst,
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controller_to_socbridge_driver => controller_to_socbridge_driver,
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socbridge_driver_to_controller => socbridge_driver_to_controller,
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ext_to_socbridge_driver => ext_to_socbridge_driver,
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socbridge_driver_to_ext => socbridge_driver_to_ext,
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ip_to_socbridge_driver => ip_to_socbridge_driver,
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socbridge_driver_to_ip => socbridge_driver_to_ip
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);
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ext_to_socbridge_driver.control(1) <= clk;
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real_clk_proc: process
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variable cycle_count :integer := 0;
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begin
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while (not done) and (cycle_count < MAX_CYCLE_COUNT) loop
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clk <= not clk;
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wait for CLK_PERIOD / 2;
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end loop;
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wait;
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end process real_clk_proc;
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reset_proc: process
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begin
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rst <= '1';
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wait for CLK_PERIOD * 3;
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rst <= '0';
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wait;
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end process reset_proc;
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command_stimulus: process
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begin
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controller_to_socbridge_driver.instruction <= NO_OP;
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controller_to_socbridge_driver.seq_mem_access_count <= 0;
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controller_to_socbridge_driver.request <= '0';
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controller_to_socbridge_driver.address <= x"00000000";
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wait until rst='0';
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for i in 100 downto 0 loop
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wait until rising_edge(clk);
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end loop;
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controller_to_socbridge_driver.instruction <= WRITE;
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controller_to_socbridge_driver.seq_mem_access_count <= 128;
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controller_to_socbridge_driver.address <= x"40000000";
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wait until rising_edge(clk);
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controller_to_socbridge_driver.request <= '1';
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wait until socbridge_driver_to_controller.is_active = '1';
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controller_to_socbridge_driver.request <= '0';
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wait until socbridge_driver_to_controller.is_active = '0';
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for i in 100 downto 0 loop
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wait until rising_edge(clk);
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end loop;
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controller_to_socbridge_driver.instruction <= READ;
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controller_to_socbridge_driver.seq_mem_access_count <= 128;
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controller_to_socbridge_driver.address <= x"40000000";
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wait until rising_edge(clk);
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controller_to_socbridge_driver.request <= '1';
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wait until socbridge_driver_to_controller.is_active = '1';
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controller_to_socbridge_driver.request <= '0';
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wait until socbridge_driver_to_controller.is_active = '0';
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done := TRUE;
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wait;
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end process command_stimulus;
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internal_stimulus: process
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variable count : integer := 1;
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begin
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ip_to_socbridge_driver.is_full_in <= '0';
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ip_to_socbridge_driver.write_enable_out <= '0';
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wait until rst = '0';
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-- stimulus goes here
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while not done loop
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wait until (rising_edge(socbridge_driver_to_ext.control(1)) or falling_edge(socbridge_driver_to_ext.control(1))) and socbridge_driver_to_ip.is_full_out = '0';
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ip_to_socbridge_driver.payload <= std_logic_vector(to_unsigned(count, 8));
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count := count + 1;
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end loop;
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wait;
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end process internal_stimulus;
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end architecture tb ;
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